Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 10/10/2025
Public
Document Table of Contents

11.6. Bridges Clocks and Resets

This section describes the clocks and resets for the bridges.

Table 331.  Bridges Clocks and Resets
Bridge Reset Clock
H2F hps2fpga_axi_reset hps2fpga_axi_clock
LWH2F lwhps2fpga_axi_reset lwhps2fpga_axi_clock
F2H fpga2hps_reset fpga2hps_clock
F2SDRAM f2sdram_axi_reset f2sdram_axi_clock
Table 332.  Maximum Bridges Clock Frequencies
Performance FPGA-to-HPS Bridge Clock (MHz) HPS-to-FPGA Bridge Clock (MHz) Lightweight HPS-to-FPGA Bridge Clock (MHz) FPGA-to-SDRAM Bridge Clock (MHz)
–1 speed grade 365 400 250 667
–2 speed grade 347 400 250 600
–3 speed grade 292 400 250 500
–4 speed grade 286 400 250 520
–5 speed grade 280 400 250 350
–6 speed grade 241 400 250 250