Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/07/2025
Public

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12.3.2.4. Reset

The reset scheme between HPS EMAC and 1G/2.5G/5G/10G Multirate Ethernet PHY is shown in the figure below.
Figure 313. Reset Connections at System Level
Table 380.   Reset Signals
Signal Name Direction Width Description PHY Configurations
reset Input 1 Active-high global reset. Assert this signal to trigger an asynchronous global reset. All MGBASE and NBASE variants
tx_digitalreset Input 1 Active-high signal. When asserted, triggers an asynchronous reset to the digital logic on the TX path and HSSI.
rx_digitalreset Input 1 Active-high signal. When asserted, triggers an asynchronous reset to the digital logic on the RX path and HSSI.
i_rst_n Input 1

Active-low asynchronous reset signal. Do not deassert until o_rst_ack_n asserts.

  • Resets the TX interface, including the TX PCS.
  • Resets the RX interface, including the RX PCS.
  • Resets the TX PMA and TX PLDIF.
  • Resets the RX PMA and RX PLDIF.

This reset leads to assertion of the o_rst_ack_n output signal.

o_rst_ack_n Output 1 Active-low asynchronous acknowledgment signal for the i_rst_n reset.

Do not deassert the i_rst_n reset until the o_rst_ack_n asserts.

i_tx_rst_n Input 1 Active-low asynchronous reset signal.

Resets the entire TX datapath, including the TX PCS, TX PMA, and TX PLDIF. Do not deassert until the o_tx_rst_ack_n asserts.

Note: In MGBASE mode, this reset impacts both TX and RX, as the TX clock is used in both direction.
o_tx_rst_ack_n Output 1 Active-low asynchronous acknowledgment signal for the i_tx_rst_n reset.

Do not deassert the i_tx_rst_n reset until o_tx_rst_ack_n asserts.

i_rx_rst_n Input 1 Active-low asynchronous reset signal.

Resets the entire RX datapath, including the RX PCS, RX PMA, and RX PLDIF. Do not deassert until o_rx_rst_ack_n asserts.

o_rx_rst_ack_n Output 1 Active-low asynchronous acknowledgment signal for the i_rx_rst_n reset.

Do not deassert the i_rx_rst_n reset until o_rx_rst_ack_n asserts.

gmii8b_tx_rst_n Input 1 Reset signal for the GMII8B adapter on the TX path.
gmii8b_rx_rst_n Input 1 Reset signal for the GMII8B adapter on the RX path.
Figure 314.  1G/2.5G/5G/10G Multirate Ethernet PHY IP Reset Sequence