Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/07/2025
Public

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13.4.2.3. F2H Bridge Firewall

There is no firewall between the F2H Bridge and the CCU. Altera highly recommends that you implement a firewall in soft logic (in the FPGA fabric) to block any unwanted traffic from the FPGA master to the HPS.

Note:

Consider the following when implementing the soft logic above:

  • If SMMU is disabled: The I/O initiator address ranges that rely on the MPFE firewall must be mapped as device non-bufferable type.
  • If SMMU is enabled: The I/O addresses must be mapped via SMMU to allow or prevent access to various address ranges.

For more information, refer to the FPGA-to-HPS CCU to Peripherals (Device Non-Bufferable) section.