Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/07/2025
Public
Document Table of Contents

1.2. MPU Revision History

Table 3.  MPU Revision History
Document Version Changes
2025.07.07
  • Updated the L3 cache information for Agilex™ 3 C-Series SoC in Table: Micro Processor Unit (MPU) Differences.
  • Added a note about cacheable atomics in MPU Arm* DynamIQ Shared Unit.
2025.04.07 Added Agilex™ 3 C-Series SoC information in MPU Differences Among Altera® SoC Device Families.
2024.11.27
2024.04.01 Initial release.