Variable Precision DSP Blocks User Guide: Agilex™ 5 FPGAs and SoCs

ID 813968
Date 9/20/2024
Public
Document Table of Contents

3.3.3.4. Output Registers for Tensor Floating-point Mode

The Agilex™ 5 variable precision DSP block features output registers for all outputs, fp32_col_{1..2}[31..0], fp32_col_{1..2}_flag[3:0], and cascade_data_out_col_{1..2}[31..0].

Figure 57. Timing Diagram for Tensor Floating-point Mode
All of the following dynamic input signals are coincident with each other and have 5 cycles of total latency between input and output.
  • load_buf_sel
  • data_in_{1..10}
  • shared_exponent_data
  • acc_en
  • zero_en

The cascade_data_in_col_{1..2} signals from the previous DSP block have 2 cycles of total latency between input and output.