Variable Precision DSP Blocks User Guide: Agilex™ 5 FPGAs and SoCs

ID 813968
Date 9/20/2024
Public
Document Table of Contents

4.2.1.2. FP16 Operation Mode Supported Register Configurations

Table 36.  Supported Register Configurations For Sum of Two FP16 Multiplication Mode
Latency Data Input Register Multiplier 1st Pipeline Register Multiplier 2nd Pipeline Register Adder Input Register Adder Pipeline Register Output Register
fp16_mult_input_clken mult_pipeline_clken mult_2nd_pipeline_clken adder_input_clken adder_pl_clken output_clken
0 Disable Disable Disable Disable Disable Disable
1 Enable Disable Disable Disable Disable Disable
1 Disable Disable Disable Disable Disable Enable
2 Enable Disable Disable Disable Disable Enable
3 Enable Disable Disable Enable Disable Enable
4 Enable Disable Disable Enable Enable Enable
≥5 Enable Disable, enable Enable Enable Enable Enable
Table 37.  Supported Register Configurations For Sum of Two FP16 Multiplication with FP32 Addition Mode
Latency Data Input Register Adder 1st Pipeline Register Adder 2nd Pipeline Register Multiplier 1st Pipeline Register Multiplier 2nd Pipeline Register Adder Input Register Adder Pipeline Register Output Register
fp32_adder_a_clken fp16_mult_input_clken fp32_adder_a_chainin_pl_clken fp32_adder_a_chainin_2nd_pl_clken mult_pipeline_clken mult_2nd_pipeline_clken adder_input_clken adder_pl_clken output_clken
0 Disable Disable Disable Disable Disable Disable Disable Disable Disable
1 Enable Enable Disable Disable Disable Disable Disable Disable Disable
1 Disable Disable Disable Disable Disable Disable Disable Disable Enable
2 Enable Enable Disable Disable Disable Disable Disable Disable Enable
≥3 Enable Enable Disable, enable Disable, enable Disable Disable Enable Disable Enable
≥4 Enable Enable Disable, enable Disable, enable Disable Disable Enable Enable Enable
≥5 Enable Enable Disable, enable Disable, enable Disable, enable Enable Enable Enable Enable
Table 38.  Supported Register Configurations For Sum of Two FP16 Multiplication with Accumulation Mode
Latency Data Input Register Adder 1st Pipeline Register Adder 2nd Pipeline Register Multiplier 1st Pipeline Register Multiplier 2nd Pipeline Register Adder Input Register Adder Pipeline Register Output Register
accumulate_clken fp16_mult_input_clken accum_pipeline_clken accum_2nd_pipeline_clken mult_pipeline_clken mult_2nd_pipeline_clken accum_adder_clken adder_input_clken adder_pl_clken output_clken
1 Disable Disable Disable Disable Disable Disable Disable Disable Disable Enable
2 Enable Enable Disable Disable Disable Disable Disable Disable Disable Enable
≥3 Enable Enable Disable, enable Disable, enable Disable Disable Disable Enable Disable Enable
≥4 Enable Enable Disable, enable Disable, enable Disable Disable Enable Enable Enable Enable
≥5 Enable Enable Disable, enable Disable, enable Disable, enable Enable Enable Enable Enable Enable
Table 39.  Supported Register Configurations For FP16 Vector One Mode
Latency Data Input Register Adder 1st Pipeline Register Adder 2nd Pipeline Register Multiplier 1st Pipeline Register Multiplier 2nd Pipeline Register Adder Input Register Adder Pipeline Register Output Register
fp32_adder_a_clken fp16_mult_input_clken fp32_adder_a_chainin_pl_clken fp32_adder_a_chainin_2nd_pl_clken mult_pipeline_clken mult_2nd_pipeline_clken adder_input_clken adder_pl_clken output_clken
0 Disable Disable Disable Disable Disable Disable Disable Disable Disable
1 Enable Enable Disable Disable Disable Disable Disable Disable Disable
1 Disable Disable Disable Disable Disable Disable Disable Disable Enable
2 Enable Enable Disable Disable Disable Disable Disable Disable Enable
≥3 Enable Enable Disable, enable Disable, enable Disable Disable Enable Disable Enable
≥4 Enable Enable Disable, enable Disable, enable Disable Disable Enable Enable Enable
≥5 Enable Enable Disable, enable Disable, enable Disable, enable Disable, enable Enable Enable Enable
Table 40.  Supported Register Configurations For FP16 Vector Two Mode
Latency Data Input Register Adder 1st Pipeline Register Adder 2nd Pipeline Register Multiplier 1st Pipeline Register Multiplier 2nd Pipeline Register Adder Input Register Adder Pipeline Register Output Register
fp32_adder_a_clken fp16_mult_input_clken fp32_adder_a_chainin_pl_clken fp32_adder_a_chainin_2nd_pl_clken mult_pipeline_clken mult_2nd_pipeline_clken adder_input_clken adder_pl_clken output_clken
0 Disable Disable Disable Disable Disable Disable Disable Disable Disable
1 Enable Enable Disable Disable Disable Disable Disable Disable Disable
1 Disable Disable Disable Disable Disable Disable Disable Disable Enable
2 Enable Enable Disable Disable Disable Disable Disable Disable Enable
≥3 Enable Enable Disable, enable Disable, enable Disable Disable Enable Enable Enable
≥4 Enable Enable Disable, enable Disable, enable Disable Disable Enable Enable Enable
Table 41.  Supported Register Configurations For FP16 Vector Three Mode
Latency Data Input Register Adder 1st Pipeline Register Adder 2nd Pipeline Register Multiplier 1st Pipeline Register Multiplier 2nd Pipeline Register Adder Input Register Adder Pipeline Register Output Register
accumulate_clken fp32_adder_a_clken fp16_mult_input_clken accum_pipeline_clken accum_2nd_pipeline_clken mult_pipeline_clken mult_2nd_pipeline_clken accum_adder_clken adder_input_clken adder_pl_clken output_clken
1 Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Enable
2 Enable Enable Enable Disable Disable Disable Disable Disable Disable Disable Enable
≥3 Enable Enable Enable Disable, enable Disable, enable Disable Disable Enable Enable Enable Enable
≥4 Enable Enable Enable Disable, enable Disable, enable Disable, enable Enable Enable Enable Enable Enable