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1. Agilex™ 5 Variable Precision DSP Blocks Overview
2. Agilex™ 5 Variable Precision DSP Blocks Architecture
3. Agilex™ 5 Variable Precision DSP Blocks Operational Modes
4. Agilex™ 5 Variable Precision DSP Blocks Design Considerations
5. Native Fixed Point DSP Agilex™ FPGA IP Core References
6. Multiply Adder Intel® FPGA IP Core References
7. ALTMULT_COMPLEX Intel® FPGA IP Core References
8. LPM_MULT Intel® FPGA IP Core References
9. LPM_DIVIDE (Divider) Intel FPGA IP Core
10. Native Floating Point DSP Agilex™ FPGA IP References
11. Native AI Optimized DSP Agilex™ FPGA IP References
12. Document Revision History for the Agilex™ 5 Variable Precision DSP Blocks User Guide
2.1.1. Input Register Bank for Fixed-point Arithmetic
2.1.2. Pipeline Registers for Fixed-point Arithmetic
2.1.3. Pre-adder for Fixed-point Arithmetic
2.1.4. Internal Coefficient for Fixed-point Arithmetic
2.1.5. Multipliers for Fixed-point Arithmetic
2.1.6. Adder or Subtractor for Fixed-point Arithmetic
2.1.7. Accumulator, Chainout Adder, and Preload Constant for Fixed-point Arithmetic
2.1.8. Systolic Register for Fixed-point Arithmetic
2.1.9. Double Accumulation Register for Fixed-point Arithmetic
2.1.10. Output Register Bank for Fixed-point Arithmetic
2.2.1. Input Register Bank for Floating-point Arithmetic
2.2.2. Pipeline Registers for Floating-point Arithmetic
2.2.3. Multipliers for Floating-point Arithmetic
2.2.4. Adder or Subtractor for Floating-point Arithmetic
2.2.5. Output Register Bank for Floating-point Arithmetic
2.2.6. Exception Handling for Floating-point Arithmetic
3.2.2.1. FP16 Supported Precision Formats
3.2.2.2. Sum of Two FP16 Multiplication Mode
3.2.2.3. Sum of Two FP16 Multiplication with FP32 Addition Mode
3.2.2.4. Sum of Two FP16 Multiplication with Accumulation Mode
3.2.2.5. FP16 Vector One Mode
3.2.2.6. FP16 Vector Two Mode
3.2.2.7. FP16 Vector Three Mode
5.1. Native Fixed Point DSP Agilex™ FPGA IP Release Information
5.2. Supported Operational Modes
5.3. Maximum Input Data Width for Fixed-point Arithmetic
5.4. Maximum Output Data Width for Fixed-point Arithmetic
5.5. Parameterizing Native Fixed Point DSP IP
5.6. Native Fixed Point DSP Agilex™ FPGA IP Signals
5.7. IP Migration
10.4.1. FP32 Multiplication Mode Signals
10.4.2. FP32 Addition or Subtraction Mode Signals
10.4.3. FP32 Multiplication with Addition or Subtraction Mode Signals
10.4.4. FP32 Multiplication with Accumulation Mode Signals
10.4.5. FP32 Vector One and Vector Two Modes Signals
10.4.6. Sum of Two FP16 Multiplication Mode Signals
10.4.7. Sum of Two FP16 Multiplication with FP32 Addition Mode Signals
10.4.8. Sum of Two FP16 Multiplication with Accumulation Mode Signals
10.4.9. FP16 Vector One and Vector Two Modes Signals
10.4.10. FP16 Vector Three Mode Signals
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4.2.1. Configurations for Input, Pipeline, and Output Registers
The configurations for the input, pipeline, and output registers are restricted due to the timing model in Agilex™ 5 devices. Therefore these registers only support certain configurations.
You must enable all registers within the same register level but you can use different clock enables. However, when port accumulate is connected to constant VCC, the register settings for accumulate_clken, accum_pipeline_clken, accum_2nd_pipeline_clken, and accum_adder_clken should be disabled to avoid register clear signal interrupting the constant VCC.
The following registers should have the same clock enable settings:
- Registers adder_input_clken and accum_adder_clken when operation_mode is set to FP32 multiplication with accumulation mode, sum of two FP16 multiplication with accumulation mode, or FP16 vector three mode.
- Registers fp16_mult_input_clken and fp32_adder_a_clken when in all FP16 operation modes except FP16 vector three mode.