GTS Serial Lite IV IP User Guide

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ID 813966
Date 10/24/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS Serial Lite IV IP User Guide: Agilex™ 5 E-Series/D-Series and Agilex™ 3 Devices 2. GTS Serial Lite IV IP Overview 3. Getting Started 4. Functional Description 5. Parameters 6. GTS Serial Lite IV IP Interface Signals 7. Designing with GTS Serial Lite IV IP 8. Document Revision History for the GTS Serial Lite IV IP User Guide
2. GTS Serial Lite IV IP Overview x
2.1. Release Information 2.2. Supported Features 2.3. IP Version Support Level 2.4. Device Speed Grade Support 2.5. Resource Utilization and Latency 2.6. Bandwidth Efficiency
3. Getting Started x
3.1. Installing and Licensing IP Cores 3.2. Specifying the IP Parameters and Options 3.3. Generated File Structure 3.4. Simulating IP Cores 3.5. Synthesizing IP Cores in Other EDA Tools 3.6. Compiling the Full Design
3.1. Installing and Licensing IP Cores x
3.1.1. IP Evaluation Mode
3.4. Simulating IP Cores x
3.4.1. Simulating and Verifying the Design
4. Functional Description x
4.1. TX Datapath 4.2. RX Datapath 4.3. GTS Serial Lite IV IP Clock Architecture 4.4. Reset and Link Initialization 4.5. Link Rate and Bandwidth Efficiency Calculation
4.1. TX Datapath x
4.1.1. TX MAC Adapter 4.1.2. Control Word (CW) Insertion 4.1.3. TX CRC 4.1.4. TX MII Encoder 4.1.5. TX PCS and PMA
4.1.2. Control Word (CW) Insertion x
4.1.2.1. Start-of-burst CW 4.1.2.2. End-of-burst CW 4.1.2.3. Alignment Paired CW 4.1.2.4. Empty-cycle CW 4.1.2.5. Idle CW 4.1.2.6. Data Word
4.2. RX Datapath x
4.2.1. RX PCS and PMA 4.2.2. RX MII Decoder 4.2.3. RX CRC 4.2.4. RX Deskew 4.2.5. RX CW Removal
4.4. Reset and Link Initialization x
4.4.1. TX Reset and Initialization Sequence 4.4.2. RX Reset and Initialization Sequence
6. GTS Serial Lite IV IP Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. MAC Signals 6.4. Transceiver Reconfiguration Signals 6.5. PMA/PCS Signals
7. Designing with GTS Serial Lite IV IP x
7.1. Reset Guidelines 7.2. Error Handling Guidelines 7.3. Analog Parameter Settings
1. About the GTS Serial Lite IV IP User Guide: Agilex™ 5 E-Series/D-Series and Agilex™ 3 Devices
2. GTS Serial Lite IV IP Overview
3. Getting Started
4. Functional Description
5. Parameters
6. GTS Serial Lite IV IP Interface Signals
7. Designing with GTS Serial Lite IV IP
8. Document Revision History for the GTS Serial Lite IV IP User Guide

4.1.2.4. Empty-cycle CW

Figure 14. Empty-cycle CW Format

When you deassert tx_avs_valid for two clock cycles during a burst, the MAC inserts an EMPTY_CYC CW paired with END/START CWs. You can use this CW when there is no data available for transmission momentarily.

When you deassert tx_avs_valid for one cycle, the IP deasserts tx_avs_valid for twice the period of tx_avs_valid deassertion to generate a pair of END/START CWs.

Table 15.   EMPTY_CYC CW Field Values
Field Value
align 0
eop 0
sop 0
usr 0
seop 0
Level Two Title