LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813929
Date 8/11/2025
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 LVDS SERDES Overview 2. Agilex™ 5 LVDS SERDES Architecture 3. Agilex™ 5 LVDS SERDES Transmitter 4. Agilex™ 5 LVDS SERDES Receiver 5. Agilex™ 5 High-Speed LVDS I/O Implementation Guide 6. Agilex™ 5 LVDS SERDES Timing 7. LVDS SERDES FPGA IP Design Examples 8. Agilex™ 5 LVDS SERDES Design Guidelines 9. Agilex™ 5 LVDS SERDES Troubleshooting Guidelines 10. LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs Archives 11. Document Revision History for the LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 LVDS SERDES Overview x
1.1. LVDS SERDES Usage Modes
2. Agilex™ 5 LVDS SERDES Architecture x
2.1. Agilex™ 5 HSIO Banks, SERDES, and DPA Locations 2.2. SERDES Blocks, Modes, and Clock Domains
3. Agilex™ 5 LVDS SERDES Transmitter x
3.1. LVDS SERDES Transmitter Blocks 3.2. Serializer 3.3. Clocking the Differential Transmitters
3.2. Serializer x
3.2.1. Serializer Bypass for DDR and SDR Operations 3.2.2. Differential I/O Bit Position
3.3. Clocking the Differential Transmitters x
3.3.1. Transmitter Output Clock Parameters Settings
3.3.1. Transmitter Output Clock Parameters Settings x
3.3.1.1. Edge-Aligned tx_outclock to tx_out 3.3.1.2. Center-Aligned tx_outclock to tx_out
4. Agilex™ 5 LVDS SERDES Receiver x
4.1. LVDS SERDES Receiver Blocks 4.2. Clocking the LVDS SERDES Receivers 4.3. LVDS SERDES Receiver Modes
4.1. LVDS SERDES Receiver Blocks x
4.1.1. Dynamic Phase Alignment Block 4.1.2. Synchronizer (DPA FIFO) 4.1.3. Data Realignment Block (Bit Slip) 4.1.4. Deserializer
4.2. Clocking the LVDS SERDES Receivers x
4.2.1. Receiver Input Clock Parameters Settings for Non-DPA Mode
4.2.1. Receiver Input Clock Parameters Settings for Non-DPA Mode x
4.2.1.1. Edge-Aligned inclock to rx_in 4.2.1.2. Center-Aligned inclock to rx_in
4.3. LVDS SERDES Receiver Modes x
4.3.1. Non-DPA Mode 4.3.2. DPA Mode 4.3.3. Soft-CDR Mode
5. Agilex™ 5 High-Speed LVDS I/O Implementation Guide x
5.1. LVDS SERDES FPGA IP 5.2. LVDS Interface with External PLL Mode 5.3. LVDS SERDES IP Initialization and Reset
5.1. LVDS SERDES FPGA IP x
5.1.1. Release Information 5.1.2. LVDS SERDES FPGA IP Features 5.1.3. LVDS SERDES IP Usage Modes 5.1.4. Planning the LVDS SERDES Interface 5.1.5. Generating the LVDS SERDES FPGA IP 5.1.6. LVDS SERDES FPGA IP Parameter Settings 5.1.7. LVDS SERDES FPGA IP Signals
5.1.5. Generating the LVDS SERDES FPGA IP x
5.1.5.1. Altera® FPGA IP Generation Output
5.1.6. LVDS SERDES FPGA IP Parameter Settings x
5.1.6.1. LVDS SERDES FPGA IP General Settings 5.1.6.2. LVDS SERDES FPGA IP Pin Settings 5.1.6.3. LVDS SERDES FPGA IP PLL Settings 5.1.6.4. LVDS SERDES FPGA IP Receiver Settings 5.1.6.5. LVDS SERDES FPGA IP Transmitter Settings 5.1.6.6. LVDS SERDES FPGA IP Clock Resource Summary
5.1.6.2. LVDS SERDES FPGA IP Pin Settings x
5.1.6.2.1. HSIO Pin Index Number and Respective Channel Pin Selection 5.1.6.2.2. Placing Channel Bytes in I/O Lanes 5.1.6.2.3. Locating the I/O Lane and Channel Pin through the Interface Planner
5.2. LVDS Interface with External PLL Mode x
5.2.1. IOPLL IP Signal Interface with LVDS SERDES IP 5.2.2. IOPLL Parameter Values for External PLL Mode 5.2.3. Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode
5.3. LVDS SERDES IP Initialization and Reset x
5.3.1. Initializing the LVDS SERDES IP in Non-DPA Mode 5.3.2. Initializing the LVDS SERDES IP in DPA Mode 5.3.3. Resetting the DPA 5.3.4. Word Boundaries Alignment
5.3.4. Word Boundaries Alignment x
5.3.4.1. Aligning Word Boundaries
6. Agilex™ 5 LVDS SERDES Timing x
6.1. LVDS SERDES FPGA IP Timing 6.2. LVDS SERDES Source-Synchronous Timing Budget
6.1. LVDS SERDES FPGA IP Timing x
6.1.1. I/O Timing Analysis 6.1.2. FPGA Timing Analysis 6.1.3. Timing Analysis for the External PLL Mode
6.1.1. I/O Timing Analysis x
6.1.1.1. Obtaining RSKM Report 6.1.1.2. Obtaining TCCS Report
6.2. LVDS SERDES Source-Synchronous Timing Budget x
6.2.1. Transmitter Channel-to-Channel Skew 6.2.2. Receiver Skew Margin
7. LVDS SERDES FPGA IP Design Examples x
7.1. LVDS SERDES IP Synthesizable Quartus® Prime Design Examples 7.2. LVDS SERDES IP Simulation Design Example
8. Agilex™ 5 LVDS SERDES Design Guidelines x
8.1. Use PLLs in Integer PLL Mode for LVDS SERDES 8.2. Use High-Speed Clock from PLL to Clock SERDES Only 8.3. Pin Placement for Differential Channels 8.4. SERDES Pin Pairs for Soft-CDR Mode 8.5. Placing LVDS SERDES Transmitters and Receivers with External PLL 8.6. Sharing LVDS SERDES I/O Lane with Other IPs
8.3. Pin Placement for Differential Channels x
8.3.1. I/O PLLs Driving LVDS SERDES Transmitter and Receiver Channels 8.3.2. Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent HSIO Bank
1. Agilex™ 5 LVDS SERDES Overview
2. Agilex™ 5 LVDS SERDES Architecture
3. Agilex™ 5 LVDS SERDES Transmitter
4. Agilex™ 5 LVDS SERDES Receiver
5. Agilex™ 5 High-Speed LVDS I/O Implementation Guide
6. Agilex™ 5 LVDS SERDES Timing
7. LVDS SERDES FPGA IP Design Examples
8. Agilex™ 5 LVDS SERDES Design Guidelines
9. Agilex™ 5 LVDS SERDES Troubleshooting Guidelines
10. LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs Archives
11. Document Revision History for the LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs

5.2.1. IOPLL IP Signal Interface with LVDS SERDES IP

Table 27.  Signal Interface between IOPLL and LVDS SERDES IPs This table lists the signal interface between the output ports of the IOPLL IP and the input ports of the LVDS SERDES IP transmitter or receiver.
From the IOPLL IP To the LVDS SERDES IP Transmitter or Receiver
outclock_periph[1:0] (serial clock output signal)
  • Configure this signal using outclk0 in the PLL.
  • Turn on Enable access to I/O Bank clock ports option under the LVDS External PLL section.

The serial clock output can only drive ext_outclock_periph[1:0] on the LVDS SERDES IP transmitter and receiver. This clock cannot drive the core logic.

ext_outclock_periph[1:0] (serial clock input to the transmitter or receiver)

outclk_2 (parallel clock output)

ext_pll_1_outclock2 (core clock to the LVDS SERDES FPGA IP)

locked

ext_pll_locked

This signal indicates when external PLL is locked. It does not indicate if SERDES is ready for initialization.

rst

pll_areset (asynchronous PLL reset port)

phout[7:0]

  • This signal is required if ext_phout[7:0] is required.

  • Configure this signal by turning on Specify VCO frequency in the PLL and specifying the Desired VCO Frequency value.
  • Turn on Enable access to PLL DPA output port.

ext_phout[7:0]

This signal is required for all transmitter or receiver modes.

phout_periph

  • Configure this signal using by turning on Specify VCO frequency in the PLL and specifying the Desired VCO Frequency value.
  • Turn on Enable access to I/O Bank clock ports option under the LVDS External PLL section.
 ext_phout_periph
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