Hard Processor System Booting User Guide: Agilex™ 3 and Agilex™ 5 SoCs
ID
813762
Date
5/09/2025
Public
1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. HPS Boot Flows
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Agilex™ 3 and Agilex™ 5 SoC Boot Flow
8. Document Revision History for the Hard Processor System Booting User Guide: Agilex™ 3 and Agilex™ 5 SoCs
4.1. Overview
4.2. Quartus® Prime Hardware Project Compilation
4.3. Bootloader Software Compilation
4.4. Programming File Generator
4.5. Configuration over JTAG
4.6. Configuration from QSPI
4.7. Configuration over AVST
4.8. Configuration via Protocol
4.9. Remote System Update
4.10. Partial Reconfiguration
4.11. Preserving SDRAM Content across HPS Resets for Agilex™ 5 Devices
4.12. QSPI Controller Ownership Selection Impact on the HPS Software
1. Introduction
Updated for: |
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Intel® Quartus® Prime Design Suite 25.1 |
This user guide describes the boot flow, boot sources, and how to generate a bitstream required for successful booting of the Agilex™ 3 and Agilex™ 5 SoCs. The details provided in this boot user guide include:
- The typical boot flows and boot stages of the Agilex™ 3 and Agilex™ 5 SoCs.
- The supported system layout for different hard processor system (HPS) boot modes.
- How to use Quartus® Prime Pro Edition to generate the configuration bitstream.