Hard Processor System Booting User Guide: Agilex™ 3 and Agilex™ 5 SoCs
ID
813762
Date
5/09/2025
Public
Visible to Intel only — GUID: vym1688590742694
Ixiasoft
1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. HPS Boot Flows
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Agilex™ 3 and Agilex™ 5 SoC Boot Flow
8. Document Revision History for the Hard Processor System Booting User Guide: Agilex™ 3 and Agilex™ 5 SoCs
4.1. Overview
4.2. Quartus® Prime Hardware Project Compilation
4.3. Bootloader Software Compilation
4.4. Programming File Generator
4.5. Configuration over JTAG
4.6. Configuration from QSPI
4.7. Configuration over AVST
4.8. Configuration via Protocol
4.9. Remote System Update
4.10. Partial Reconfiguration
4.11. Preserving SDRAM Content across HPS Resets for Agilex™ 5 Devices
4.12. QSPI Controller Ownership Selection Impact on the HPS Software
Visible to Intel only — GUID: vym1688590742694
Ixiasoft
4. Creating the Configuration Files
There are several different configuration methods available:
- Configuration over JTAG
- Configuration from QSPI
- Configuration over AVST
- Configuration via Protocol
- Remote System Update (RSU)
This chapter describes how to create the configuration files for all these configuration methods.
Section Content
Overview
Quartus Prime Hardware Project Compilation
Bootloader Software Compilation
Programming File Generator
Configuration over JTAG
Configuration from QSPI
Configuration over AVST
Configuration via Protocol
Remote System Update
Partial Reconfiguration
Preserving SDRAM Content across HPS Resets for Agilex 5 Devices
QSPI Controller Ownership Selection Impact on the HPS Software