Hard Processor System Booting User Guide: Agilex™ 3 and Agilex™ 5 SoCs

ID 813762
Date 5/09/2025
Public
Document Table of Contents

7.2. Debugging the HPS Bootloader

You can debug the bootloader by using Arm* DS for Intel® SoC FPGA or Ashling RiscFree* IDE for Intel FPGAs Arm* -based HPS and RISC-V based Nios® V processors. In order to do that, you need a JTAG connection, so you must enable the HPS Debug Access Port to be accessible through either the SDM or HPS pins.

For more information, refer to the Device and Pin Options section.