Hard Processor System Booting User Guide: Agilex™ 3 and Agilex™ 5 SoCs
ID
813762
Date
5/09/2025
Public
1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. HPS Boot Flows
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Agilex™ 3 and Agilex™ 5 SoC Boot Flow
8. Document Revision History for the Hard Processor System Booting User Guide: Agilex™ 3 and Agilex™ 5 SoCs
4.1. Overview
4.2. Quartus® Prime Hardware Project Compilation
4.3. Bootloader Software Compilation
4.4. Programming File Generator
4.5. Configuration over JTAG
4.6. Configuration from QSPI
4.7. Configuration over AVST
4.8. Configuration via Protocol
4.9. Remote System Update
4.10. Partial Reconfiguration
4.11. Preserving SDRAM Content across HPS Resets for Agilex™ 5 Devices
4.12. QSPI Controller Ownership Selection Impact on the HPS Software
4.2.1. Device and Pin Options
The device and pin options can be accessed from Quartus® Prime, by going to Assignments > Device > Device and Pin Options. The most important options related to configuration and HPS boot are:
- General > Configuration Clock Source—allows using an internal oscillator or an external input clock for configuration purposes.
- Configuration > Configuration Scheme—allows selecting the configuration source:
- Active Serial x4
- AVST x8
- AVST x16
Note: The AVST x16 configuration scheme cannot be used in designs that include the HPS. HPS-EMIF signals and AVST x16 signals are both located in the same bank, therefore, they cannot be used simultaneously. The AVST x8 mode uses dedicated SDM I/O pins, therefore, it can be used in designs that include the HPS.
- Configuration > Active Serial Clock Source—allows selecting the QSPI clock speed when Active Serial x4 mode is selected
- Configuration > Configuration Pin Options—allows selecting SDM pin behavior for configuration purposes
- Configuration > HPS/FPGA Configuration Order—allows selecting FPGA Configuration First (called After INIT_DONE) or HPS Boot First (called HPS First) modes.
- Configuration > HPS Debug Access Port (DAP)—allows the HPS JTAG port to be connected to HPS Pins, SDM Pins, or Disabled. It is typically connected to SDM pins, so you can have a single JTAG connection covering both SDM and HPS.
- Configuration > QSPI Ownership—allows the selection of QSPI controller ownership, either for the HPS or the SDM. At power up, the QSPI controller ownership is assigned to the SDM. However, the HPS can request the ownership by sending the QSPI_DIRECT command through the HPS-to-SDM mailbox. This setting controls whether the ownership request from the HPS is granted or rejected.
- QSPI Ownership: SDM. The QSPI_DIRECT command from the HPS is actively rejected. This means the HPS cannot perform direct access to the QSPI controller. This ensures that the SDM retains ownership of the QSPI so that it can support features that depend on this ownership.
- QSPI Ownership: HPS. The QSPI_DIRECT command from the HPS is accepted, and the HPS takes control of the QSPI controller. This means the HPS can perform direct access to the QSPI controller, enabling it to support features that depend on this access.
- CvP Settings > Configuration via Protocol—can be selected as Initialization and Update or Off.
The following information focus on the QSPI Selection Configuration option:
- Quartus Prime 25.1 supports this configuration option, implementing it to enhance security in features like attestation and those relying on off-chip storage (e.g., QSPI flash device) of encryption keys, which require SDM ownership of the QSPI controller.
- The key point is that you configure this setting to support the QSPI controller features required by your project.
Note: The QSPI Ownership selection feature lacks backward compatibility. Therefore, for Remote System Update, do not use QSPI image bitstreams created before the 25.1 release alongside those created with 25.1 and later releases.
For more information, refer to:
- Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs
- Device Configuration User Guide Agilex™ 3 FPGAs and SoCs
- A.2.2.1. Feature Availability under SDM/HPS Ownership of Quad SPI Controller in the Hard Processor System Technical Reference Manual: Agilex 5 SoCs for information about the features supported in each of the configuration options.
Related Information