Hard Processor System Booting User Guide: Agilex™ 3 and Agilex™ 5 SoCs
ID
813762
Date
5/09/2025
Public
1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. HPS Boot Flows
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Agilex™ 3 and Agilex™ 5 SoC Boot Flow
8. Document Revision History for the Hard Processor System Booting User Guide: Agilex™ 3 and Agilex™ 5 SoCs
4.1. Overview
4.2. Quartus® Prime Hardware Project Compilation
4.3. Bootloader Software Compilation
4.4. Programming File Generator
4.5. Configuration over JTAG
4.6. Configuration from QSPI
4.7. Configuration over AVST
4.8. Configuration via Protocol
4.9. Remote System Update
4.10. Partial Reconfiguration
4.11. Preserving SDRAM Content across HPS Resets for Agilex™ 5 Devices
4.12. QSPI Controller Ownership Selection Impact on the HPS Software
1.2. Agilex™ 3 and Agilex™ 5 SoC Boot Overview
The Agilex™ 3 and Agilex™ 5 SoC combines an FPGA with a hard processor system (HPS) that is capable of booting baremetal and operating systems such as Linux* and Zephyr* .
You can choose between two different methods of booting:
- FPGA Configuration First Mode— When you select the FPGA First option, the SDM fully configures the FPGA, then configures the HPS SDRAM pins, loads the HPS first-stage bootloader (FSBL) and takes the HPS out of reset.
Note: The FPGA and all of the I/Os are fully configured before the HPS is released from reset. Thus, when the HPS boots, the FPGA is in user mode and is ready to interact with the HPS.
- HPS Boot First Mode—When you select the HPS First option, the SDM first configures the HPS SDRAM pins, loads the HPS FSBL and takes the HPS out of reset. Then the HPS configures the FPGA I/O and FPGA fabric at a later time.
Note: This mode is also referred to as Early I/O Release Mode or Early I/O Configuration. After power-on, the device configures a minimal amount of I/O required by the HPS before releasing the HPS from reset. This mode allows the HPS to boot quickly without having to wait for the full fabric configuration to complete. Subsequently, the HPS may trigger an FPGA configuration request during the SSBL or OS stage.
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