Hard Processor System Component Reference Manual: Agilex™ 5 SoCs
ID
813752
Date
11/25/2024
Public
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2.1. Parameterizing the HPS Component
2.2. HPS-FPGA Interfaces
2.3. SDRAM
2.4. HPS Clocks, Reset, Power
2.5. I/O Delays
2.6. Pin Mux and Peripherals
2.7. Generating and Compiling the HPS Component
2.8. Using the Address Span Extender Component
2.9. Configuring the Agilex™ 5 Hard Processor System Component Revision History
2.2.1.1. Enable MPU Standby and Event Signals
2.2.1.2. Enable General Purpose Signals
2.2.1.3. Enable Debug APB* Interface
2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events
2.2.1.5. Enable SWJ-DP JTAG Interface
2.2.1.6. Enable FPGA Cross Trigger Interface
2.2.1.7. Enable AMBA* Trace Bus (ATB)
3.1. Simulation Flows
3.2. Running the Simulation of the Design Examples
3.3. Clock and Reset Interface
3.4. FPGA-to-HPS AXI* Subordinate Interface
3.5. FPGA-to-SDRAM AXI* Subordinate Interface
3.6. HPS-to-FPGA AXI* Initiator Interface
3.7. Lightweight HPS-to-FPGA AXI* Initiator Interface
3.8. Simulating the Agilex™ 5 HPS Component Revision History
2.2.1.7. Enable AMBA* Trace Bus (ATB)
The AMBA* Trace Bus on the FPGA boundary allow ATB compatible sources to be enabled as soft IP on fabric to transport messages generated on the fabric to the CoreSight trace infrastructure.
Turning on the Enable AMBA* Trace Bus option enables the f2atb_trace_bus conduit, which is comprised of the following signals:
Signal Name | Interface Type |
---|---|
fpga_atb_atclk |
Clock Input |
fpga_atb_atreset_n |
Reset Input |
fpga_atb_atdata[31…0] |
Conduit |
fpga_atb_atvalid |
Conduit |
fpga_atb_atready |
Conduit |
fpga_atb_atid[6…0] |
Conduit |
fpga_atb_atbytes[1…0] |
Conduit |
fpga_atb_afvalid |
Conduit |
fpga_atb_afready |
Conduit |
fpga_atb_syncreq |
Conduit |