Hard Processor System Component Reference Manual: Agilex™ 5 SoCs
ID
813752
Date
11/25/2024
Public
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2.1. Parameterizing the HPS Component
2.2. HPS-FPGA Interfaces
2.3. SDRAM
2.4. HPS Clocks, Reset, Power
2.5. I/O Delays
2.6. Pin Mux and Peripherals
2.7. Generating and Compiling the HPS Component
2.8. Using the Address Span Extender Component
2.9. Configuring the Agilex™ 5 Hard Processor System Component Revision History
2.2.1.1. Enable MPU Standby and Event Signals
2.2.1.2. Enable General Purpose Signals
2.2.1.3. Enable Debug APB* Interface
2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events
2.2.1.5. Enable SWJ-DP JTAG Interface
2.2.1.6. Enable FPGA Cross Trigger Interface
2.2.1.7. Enable AMBA* Trace Bus (ATB)
3.1. Simulation Flows
3.2. Running the Simulation of the Design Examples
3.3. Clock and Reset Interface
3.4. FPGA-to-HPS AXI* Subordinate Interface
3.5. FPGA-to-SDRAM AXI* Subordinate Interface
3.6. HPS-to-FPGA AXI* Initiator Interface
3.7. Lightweight HPS-to-FPGA AXI* Initiator Interface
3.8. Simulating the Agilex™ 5 HPS Component Revision History
2.2.1.3. Enable Debug APB* Interface
The debug Advanced Peripheral Bus ( APB* ) interface allows debug components in the FPGA fabric to access debug components in the HPS.
For more information, refer to the CoreSight Debug and Trace chapter in the Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs.
Turning on this option enables the following interfaces and signals:
Signal Name | Interface Type |
---|---|
cs_debug_apd_clock_clk | Clock Input |
cs_debug_apd_reset_reset_n | Reset Input |
cs_dbg_apb_paddr[16…0] | APB Requester |
cs_dbg_apb_penable | APB Requester |
cs_dbg_apb_prdata[31…0] | APB Requester |
cs_dbg_apb_pready | APB Requester |
cs_dbg_apb_psel[15…0] | APB Requester |
cs_dbg_apb_pslverr | APB Requester |
cs_dbg_apb_pwdata[31…0] | APB Requester |
cs_dbg_apb_pwrite | APB Requester |
cs_dbg_apb_dbg_apb_disable | Conduit |
cs_dbg_apb_pclken | Conduit |
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