1G/2.5G/5G/10G Multirate Ethernet PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

Download PDF
ID 813667
Date 8/04/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY IP for Agilex™ 3 and Agilex™ 5 Devices 2. Getting Started 3. Functional Description 4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY IP 5. Interface Signals 6. Configuration Registers 7. Debug Checklist 8. 1G/2.5G/5G/10G Multirate Ethernet PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives 9. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY IP for Agilex™ 3 and Agilex™ 5 Devices x
1.1. Release Information 1.2. Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization
2. Getting Started x
2.1. Introduction to IP 2.2. Installing and Licensing IPs 2.3. Specifying the IP Core Parameters and Options 2.4. Generated File Structure 2.5. Simulating IPs 2.6. Integrating Your IP Core in Your Design
2.2. Installing and Licensing IPs x
2.2.1. Altera FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Adding the GTS System PLL Clocks IP
3. Functional Description x
3.1. Architecture 3.2. Dynamic Reconfiguration Flow 3.3. Clocking and Reset Sequence 3.4. Timing Constraints 3.5. Operation Speed Switching 3.6. USXGMII 3.7. Fmax Requirement
3.1. Architecture x
3.1.1. 2.5G, 1G/2.5G, 1G/2.5G/10G (MGBASE) 3.1.2. 10M/100M/1G/2.5G/5G/10G (USXGMII) 3.1.3. 1G/2.5G/10G MGBASE PCS only
3.2. Dynamic Reconfiguration Flow x
3.2.1. RTL Generation using Dynamic Reconfiguration IP
3.2.1. RTL Generation using Dynamic Reconfiguration IP x
3.2.1.1. Step 1: Generating the 1G/2.5G/5G/10G Multirate Ethernet PHY IP 3.2.1.2. Step 2: QSF settings and Dynamic Reconfiguration (DR) profile assignments 3.2.1.3. Step 3: RTL Generation using Quartus® Prime Pro Edition Tool 3.2.1.4. Step 4: Instantiate the IP top file with the GTS Dynamic Reconfiguration Controller IP
3.3. Clocking and Reset Sequence x
3.3.1. Clocking 3.3.2. Reset Sequence
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY IP x
4.1. Core Configuration 4.2. Analog Parameters
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. Serial Interface Signals 5.4. Avalon Memory-Mapped Interface Signals 5.5. XGMII Signals 5.6. GMII Signals 5.7. PHY Status Signals 5.8. Transceiver Mode and Operating Speed Signals 5.9. Transceiver Status and Reconfiguration Signals 5.10. GTS Reset Sequencer Signals 5.11. Dynamic Reconfiguration Controller Interface Signals
5.6. GMII Signals x
5.6.1. 1G/2.5G/10G MGBASE PCS Only PMA Interface
6. Configuration Registers x
6.1. Register Map 6.2. PHY Registers
7. Debug Checklist x
7.1. Pre-Debugging Process 7.2. Clock Frequency 7.3. Recommended Reset Handling 7.4. Signals for Signal Tap
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY IP for Agilex™ 3 and Agilex™ 5 Devices
2. Getting Started
3. Functional Description
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY IP
5. Interface Signals
6. Configuration Registers
7. Debug Checklist
8. 1G/2.5G/5G/10G Multirate Ethernet PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives
9. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

1.2. Features

Table 2.   1G/2.5G/5G/10G Multirate Ethernet PHY IP Core Features
Feature Description
Operating speeds 10M, 100M, 1G, 2.5G, 5G, and 10G.
MAC-side interface 8-bit GMII for 10M/100M/1G/2.5G (MGBASE).
16-bit GMII for 10M/100M/1G/2.5G (MGBASE).
32-bit XGMII for 10M/100M/1G/2.5G/5G/10G (USXGMII/NBASE).
64-bit XGMII for 10G (MGBASE).
Network-side interface 1.25 Gbps for 1G (MGBASE) and 10M/100M/1G (SGMII).
3.125 Gbps for 2.5G (MGBASE).
10.3125 Gbps for 10M/100M/1G/2.5G/5G/10G (USXGMII/NBASE) and 10G (MGBASE).
Avalon® memory-mapped interface Provides access to the configuration registers of the PHY.
PCS function 1000BASE-X for 1GbE and 2.5GbE.
SGMII (10M/100M/1G) for 1GbE/2.5GbE and 1GbE/2.5GbE/10GbE.
10GBASE-R for 10G (MGBASE).
USXGMII PCS for 10M/100M/1G/2.5G/5G/10G (USXGMII).
PCS only mode Supported for 1G/2.5G/10G (MGBASE) variant with and without SGMII bridge enabled.
Auto-negotiation

Not supported.
IEEE 1588v2
  • Provides the required latency to the MAC if the MAC enables the IEEE 1588v2 feature.
  • Supported in 1G/2.5G, 1G/2.5G/10G, and 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration.
Note: For the 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration, the provided latency is applicable only for 100M, 1G, 2.5G, 5G, and 10G modes.
Sync-E

Not supported.
Dynamic Reconfiguration Supported in 1G/2,5G and 1G/2.5G/10G MGBASE variants
Table 3.  Supported Line-side Modes for 1G/2.5G/5G/10G Multirate Ethernet PHY IP for Agilex™ 3 and Agilex™ 5 Devices
Line-side Protocol Low Latency Ethernet 10G MAC Configurations 1G/2.5G/5G/10G Multirate Ethernet PHY Configurations
MGBASE (via GMII) 10M/100M/1G/2.5G (MGBASE) without IEEE 1588v2 1G/2.5G (MGBASE)
1G/2.5G (MGBASE) with IEEE 1588v2 1G/2.5G (MGBASE)
MGBASE (via XGMII) 10M/100M/1G/2.5G/10G without IEEE 1588v2 1G/2.5G/10G (MGBASE)
MGBASE (2.5G only) 1G/2.5G (MGBASE) without IEEE 1588v2 2.5G (MGBASE)
1G/2.5G/10G with IEEE 1588v2 1G/2.5G/10G
1G/2.5G (MGBASE) with IEEE 1588v2 2.5G (MGBASE)
NBASE (via USXGMII) 10M/100M/1G/2.5G/5G/10G (USXGMII) without IEEE 1588v2 10M/100M/1G/2.5G/5G/10G (NBASE)
10M/100M/1G/2.5G/5G/10G (USXGMII) with IEEE 1588v2 10M/100M/1G/2.5G/5G/10G (NBASE)
MGBASE PCS only 10M/100M/1G/2.5G/10G (MGBASE) without IEEE 1588v2 1G/2.5G/10G (MGBASE)
  • 10M/100M/1G/2.5G rates– soft PCS part of 1G/2.5G/5G/10G Multirate Ethernet PHY IP (with SGMII bridge enabled)
  • 10G rate–Hard PCS, part of GTS Transceiver PHY IP. Refer to GTS Transceiver PHY User Guide.
Related Information
Level Two Title