Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813652
Date 11/25/2024
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Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40G Ethernet Intel® FPGA IP 2. Low Latency 40G Ethernet Intel® FPGA IP Parameters 3. Getting Started 4. Functional Description 5. Clocking and Reset Requirements 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs 9. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the Low Latency 40G Ethernet Intel® FPGA IP x
1.1. Low Latency 40G Ethernet Intel® FPGA IP Supported Features 1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support 1.3. Resource Utilization 1.4. Release Information
1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support x
1.2.1. Low Latency 40G Ethernet Intel® FPGA IP Device Family Support 1.2.2. Low Latency 40G Ethernet Intel® FPGA IP Device Speed Grade Support
3. Getting Started x
3.1. Introduction to Intel® FPGA IP 3.2. Installing and Licensing Intel® FPGA IPs 3.3. Specifying the IP Parameters and Options 3.4. Simulating the IP 3.5. Generated File Structure 3.6. Integrating Your IP in Your Design 3.7. Testbench 3.8. Compiling the Full Design and Programming the FPGA
3.6. Integrating Your IP in Your Design x
3.6.1. Pin Assignments 3.6.2. Placement Settings
3.7. Testbench x
3.7.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Low Latency 40G Ethernet Intel® FPGA IP Functional Description 4.2. GTS Transceiver Configuration 4.3. TX Datapath 4.4. RX Datapath 4.5. Flow Control 4.6. Link Fault Signaling Interface
4.3. TX Datapath x
4.3.1. TX MAC 4.3.2. TX PCS 4.3.3. PMA
4.3.1. TX MAC x
4.3.1.1. Preamble Insertion 4.3.1.2. Frame Padding 4.3.1.3. Inter-Packet Gap Generation and Insertion 4.3.1.4. Frame Check Sequence (CRC-32) Insertion 4.3.1.5. TX Avalon® Streaming Filter
4.4. RX Datapath x
4.4.1. RX MAC 4.4.2. RX PCS
4.4.1. RX MAC x
4.4.1.1. IP Core Preamble Processing 4.4.1.2. IP Core CRC Checking and Dynamic Forwarding 4.4.1.3. IP Core Strict SFD Checking 4.4.1.4. Length/Type Field Processing
4.4.1.4. Length/Type Field Processing x
4.4.1.4.1. Frame Type Checking 4.4.1.4.2. Length Checking
4.5. Flow Control x
4.5.1. TX Pause/PFC Flow Control Transmission 4.5.2. XON/XOFF Pause Frames
5. Clocking and Reset Requirements x
5.1. Clocks 5.2. Reset Requirements
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. TX PCS Interface to User Logic 6.4. RX PCS Interface to User Logic 6.5. GTS Transceivers Signals 6.6. GTS Transceiver Reconfiguration Signals 6.7. Avalon® Memory-Mapped Management Interface 6.8. Miscellaneous Status and Debug Signals 6.9. Reset Signals 6.10. Clocks 6.11. Flow Control Interface 6.12. GTS Reset Sequencer Intel® FPGA IP
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control 7.5. Statistics Counters 7.6. Shadow Register
1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

9. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

Date Quartus® Prime Version IP version Changes
2024.11.25 24.3 4.0.0
  • Added information that the Low Latency 40G Ethernet Intel® FPGA IP now supports the MAC, PCS, and PMA and PCS and PMA variants.
  • Removed the note mentioning the restricted device support for Agilex™ 5 D-Series FPGAs and SoCs in Quartus® Prime Pro Edition software.
  • Removed note indicating that the IP does not support speed grade of '6' in Table: Slowest Supported Device Speed Grades.
  • Updated the release information in Table: Low Latency 40G Ethernet Intel® FPGA IP (intel_eth_e40) for Current Release Information.
  • Added Select USER MAC mode in Table: Low Latency 40G Ethernet Intel® FPGA IP Parameters: Main Tab.
  • Added Table: Reset Signal Functions in Reset Requirements topic.
  • Added more information about transmit frame for l2_txstatus_data and l2_txstatus_error signals in Table: Avalon® Streaming Interface TX MAC Interface Signals.
  • Added TX PCS Interface to User Logic and RX PCS Interface to User Logic topics.
  • Added tx_mii_rst_n and rx_mii_rst_n signals in Table: Reset Signals.
  • Updated the following figures:
    • Low Latency 40G Ethernet Intel® FPGA IP Block Diagram
    • Clocks
    • Low Latency 40G Ethernet Intel® FPGA IP Signals and Interfaces Block Diagram
2024.07.22 24.2 3.0.0
  • Added note indicating that the IP does not support speed grade of '6' in Table: Slowest Supported Device Speed Grades.
  • Updated the release information in Table: Low Latency 40G Ethernet Intel® FPGA IP (intel_eth_e40) for Current Release Information.
  • Added analog parameter section in Low Latency 40G Ethernet Intel® FPGA IP Parameters.
  • Updated the following parameters in Table: Low Latency 40G Ethernet Intel® FPGA IP Parameters: Main Tab:
    • Added Enable cdr dedicated clk option
    • Added 312.5 MHz and 322.265625 MHz as PHY reference frequencies
  • Added IPUpgardeLog.xml in Table: IP Generated Files.
  • Added cdr_divclk signals in Table: Transceiver Signals.
  • Added reconfig_readdatavalid signals in Table: Transceiver Reconfiguration Signals.
  • Updated the following figures:
    • Clocks
    • Reset Sequence
    • Low Latency 40G Ethernet Intel® FPGA IP Signals and Interfaces Block Diagram
2024.04.01 24.1 2.1.0 Initial release.
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