Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
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7. Control, Status, and Statistics Register Descriptions
This section provides information about the memory-mapped registers. You access these registers using the IP's Avalon® memory-mapped control and status interface. The registers use 32-bit addresses; they are not byte addressable.
Write operations to a read-only register field have no effect. Read operations that address a Reserved register return an unspecified result. Write operations to Reserved registers have no effect. Accesses to registers that do not exist in your IP variation, or to register bits that are not defined in your IP variation, have an unspecified result. You should consider these registers and register bits Reserved. Although you can only access registers in 32-bit read and write operations, you should not attempt to write meaning to values in undefined register bits.
| Word Offset | Register Type |
|---|---|
| 0x300-0x3FF | PHY registers |
| 0x400-0x4FF | TX MAC registers |
| 0x500-0x5FF | RX MAC registers |
| 0x600-0x6FF | TX flow control |
| 0x700-07xFF | RX flow control |
| 0x800-0x8FF | Statistics Counter registers - TX direction |
| 0x900-0x9FF | Statistics Counter registers - RX direction |
In PCS and PMA mode, only the PHY registers (0x300-0x3FF) address range is valid. In the PCS and PMA variant, the address range other than the “PHY registers” returns "0xDEADC0DE” in case of read. However, it ignores the writes and generates waitrequest for both read and write to complete the access.