Logic Array Blocks and Adaptive Logic Modules User Guide: Agilex™ 5 FPGAs and SoCs
ID
813159
Date
2/28/2025
Public
2. Hyperflex® Register
The Agilex™ 5 device family is based on the Hyperflex® core architecture.
The Agilex™ 5 LAB contains Hyperflex® registers and other features designed to facilitate retiming. Hyperflex® registers are available in ALMs and carry chains. As shown in the Agilex™ 5 ALM Connection Details figure, the Hyperflex® registers are located on the synchronous clear and clock enable inputs to increase or reduce path delay. All the Hyperflex® registers can be enabled and are controlled by the Quartus® Prime software during retiming.