Logic Array Blocks and Adaptive Logic Modules User Guide: Agilex™ 5 FPGAs and SoCs
ID
813159
Date
2/28/2025
Public
3.1.1. MLAB
Each MLAB supports a maximum of 640 bits of simple dual-port SRAM. You can configure each ALM in an MLAB as a 32 (depth) x 2 (width) memory block, resulting in a configuration of 32 (depth) x 20 (width) simple dual-port SRAM block.
Figure 2. Agilex™ 5 LAB and MLAB Structure