Logic Array Blocks and Adaptive Logic Modules User Guide: Agilex™ 5 FPGAs and SoCs
ID
813159
Date
2/28/2025
Public
3.1.3. Carry Chain Interconnects
There is a dedicated carry chain path between the ALMs. Agilex™ 5 FPGAs include an enhanced interconnect structure in LABs for routing carry chains for efficient arithmetic functions. These ALM-to-ALM connections bypass the local interconnect.
The Hyperflex® registers are added to the carry chain to enable flexible retiming across a chain of LABs and the Quartus® Prime Compiler automatically takes advantage of these resources to improve utilization and performance.
Figure 4. Carry Chain Interconnects