AXI Streaming Intel® FPGA IP for PCI Express* User Guide

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ID 790711
Date 4/12/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Features 3. Getting Started with the AXI Streaming Intel® FPGA IP for PCI Express* 4. IP Architecture and Functional Description 5. AXI Streaming Intel® FPGA IP for PCI Express* Parameters 6. Interfaces and Signals 7. Register Descriptions 8. Document Revision History for the AXI Streaming Intel® FPGA IP for PCI Express* User Guide A. Specifications B. Simulating the Design Example
1. Introduction x
1.1. Goal of the AXI Streaming Intel® FPGA IP for PCI Express* User Guide 1.2. Intended Audience for the AXI Streaming Intel® FPGA IP for PCI Express* User Guide 1.3. What is PCI Express* ? 1.4. What are the Intel® FPGA IPs for PCI Express* ? 1.5. What is the AXI Streaming Intel® FPGA IP for PCI Express* ? 1.6. Example Use Models 1.7. Design Flow Requirements
1.7. Design Flow Requirements x
1.7.1. Design Software 1.7.2. Hardware
2. Features x
2.1. Supported Features 2.2. Device Family Support 2.3. Performance
3. Getting Started with the AXI Streaming Intel® FPGA IP for PCI Express* x
3.1. Download and Install Quartus Software 3.2. Obtain and Install Intel FPGA IPs and Licenses 3.3. Configure and Generate the AXI Streaming Intel® FPGA IP for PCI Express* 3.4. Instantiate and Connect the AXI Streaming Intel® FPGA IP for PCI Express* Interfaces 3.5. Simulate the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant 3.6. Compile the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant 3.7. Software Drivers for AXI Streaming Intel® FPGA IP for PCI Express* IP Variant 3.8. Build the Application for the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant 3.9. Verification with the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant 3.10. Debugging with the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant
3.4. Instantiate and Connect the AXI Streaming Intel® FPGA IP for PCI Express* Interfaces x
3.4.1. Clocking and Resets 3.4.2. Application Packet Datapath 3.4.3. Enabling Additional Features 3.4.4. Enabling Optional Interfaces
3.5. Simulate the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant x
3.5.1. Simulating the Design Example
3.5.1. Simulating the Design Example x
3.5.1.1. Steps to Run Simulations
3.5.1.1. Steps to Run Simulations x
3.5.1.1.1. VCS* Simulator
3.7. Software Drivers for AXI Streaming Intel® FPGA IP for PCI Express* IP Variant x
3.7.1. Installing the Linux Kernel Driver
3.8. Build the Application for the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant x
3.8.1. Running the Design Example
3.8.1. Running the Design Example x
3.8.1.1. Running the PIO Design Example
3.10. Debugging with the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant x
3.10.1. Debugging Link Training Issues 3.10.2. Debugging Data Transfer and Performance Issues
3.10.1. Debugging Link Training Issues x
3.10.1.1. Operating System Tools and Utilities 3.10.1.2. Signal Tap Logic Analyzer 3.10.1.3. Additional Debug Tools
3.10.2. Debugging Data Transfer and Performance Issues x
3.10.2.1. Advanced Error Reporting (AER) 3.10.2.2. Second-Level Debug Tools
4. IP Architecture and Functional Description x
4.1. Clocks and Resets 4.2. PCIe Hard IP (HIP) 4.3. HIP Interface (IF) Adaptor 4.4. Application Error Reporting 4.5. Debug Toolkit and Hard IP (HIP) Reconfiguration Interface 4.6. Configuration Space Extension 4.7. Control Shadow 4.8. Configuration Intercept Interface 4.9. Power Management 4.10. Legacy Interrupt 4.11. Credit Handling 4.12. Completion Timeout 4.13. Transaction Ordering 4.14. Page Request Service (PRS) Events 4.15. TX Non-Posted Metering Requirement on Application 4.16. MSI Pending 4.17. D-State Status 4.18. Configuration Retry Status Enable 4.19. AXI-Streaming Interface 4.20. Precision Time Measurement (PTM) [F/R-Tiles Only]
5. AXI Streaming Intel® FPGA IP for PCI Express* Parameters x
5.1. Parameter Editor Parameters
6. Interfaces and Signals x
6.1. Overview 6.2. Clocks and Resets 6.3. Application Packet Interface 6.4. Configuration Extension Bus Interface 6.5. Configuration Intercept Interface 6.6. Function Level Reset Interface 6.7. Control Shadow Interface (st_ctrlshadow) 6.8. Completion Timeout Interface (st_cplto) 6.9. Miscellaneous Signals 6.10. Control and Status Register Responder Interface (lite_csr) 6.11. VF Error Flag Interface (vf_err/sent_vfnonfatalmsg) 6.12. VIRTIO PCI* Configuration Access Interface 6.13. Serial Data Signals
6.2. Clocks and Resets x
6.2.1. Interface Clock Signals 6.2.2. Interface Reset Signals
6.3. Application Packet Interface x
6.3.1. Header Format 6.3.2. Prefix Format 6.3.3. Function Number Format 6.3.4. BAR Number Format 6.3.5. Data and Header Packing Schemes 6.3.6. Application Packet Transmit Interface (st_tx) 6.3.7. Application Packet Receive Interface (st_rx) 6.3.8. Flow Control Credit Handling
6.3.5. Data and Header Packing Schemes x
6.3.5.1. HIP Native Mode Packing 6.3.5.2. Compact Packing 6.3.5.3. Simple Packing
6.3.5.1. HIP Native Mode Packing x
6.3.5.1.1. Application Logic Guidelines for the AXI Streaming TX Interface in HIP Native Mode (R-Tile) 6.3.5.1.2. Application Logic Guidelines for the AXI Streaming RX Interface in HIP Native Mode
6.3.5.2. Compact Packing x
6.3.5.2.1. Application Logic Guidelines for the AXI Streaming TX Interface in Compact Mode (P/R-Tiles) 6.3.5.2.2. Application Logic Guidelines for the AXI Streaming RX Interface in Compact Mode (P/R-Tiles)
6.3.5.3. Simple Packing x
6.3.5.3.1. Application Logic Guidelines for the AXI Streaming TX Interface in Simple Mode (P/R-Tiles) 6.3.5.3.2. Application Logic Guidelines for the AXI Streaming RX Interface in Simple Mode (P/R-Tiles)
6.3.8. Flow Control Credit Handling x
6.3.8.1. Application Transmit Flow Control Credit Interface (st_txcrdt) 6.3.8.2. Application Receive Flow Control Credit Interface (st_rxcrdt) (R-Tile Only)
6.4. Configuration Extension Bus Interface x
6.4.1. Configuration Extension Bus Request Interface (st_cebreq) 6.4.2. Configuration Extension Bus Response Interface (st_cebresp)
6.5. Configuration Intercept Interface x
6.5.1. Configuration Intercept Request Interface (st_ciireq) 6.5.2. Configuration Intercept Response Interface (st_ciiresp)
6.6. Function Level Reset Interface x
6.6.1. Function Level Reset Received Interface (st_flrrcvd) 6.6.2. Function Level Reset Completion Interface (st_flrcmpl)
6.12. VIRTIO PCI* Configuration Access Interface x
6.12.1. VIRTIO PCI* Config Access Request Interface (st_virtio_pcicfgreq) 6.12.2. VIRTIO PCI* Config Access Completion Interface (st_virtio_pcicfgcmpl)
7. Register Descriptions x
7.1. Register Address Map 7.2. PCIe Configuration Space 7.3. AXI Streaming Intel® FPGA IP for PCI Express* Soft Register Address Map
7.2. PCIe Configuration Space x
7.2.1. PCIe Configuration Space Registers
7.3. AXI Streaming Intel® FPGA IP for PCI Express* Soft Register Address Map x
7.3.1. AXI Streaming Intel® FPGA IP for PCI Express* Control Registers 7.3.2. IP Debug Registers 7.3.3. IP Performance Monitor Registers
7.3.1. AXI Streaming Intel® FPGA IP for PCI Express* Control Registers x
7.3.1.1. AXI Streaming Intel® FPGA IP for PCI Express* Version 7.3.1.2. AXI Streaming Intel® FPGA IP for PCI Express* Features 7.3.1.3. AXI Streaming Intel® FPGA IP for PCI Express* Interface Attributes 7.3.1.4. ERROR GEN CTRL 7.3.1.5. ERROR GEN ATTR 7.3.1.6. ERROR TLP Header DW0-3 7.3.1.7. ERROR TLP Prefix 7.3.1.8. HOT PLUG GEN CTRL 7.3.1.9. POWER MANAGEMENT CTRL 7.3.1.10. LEGACY INTERRUPT CTRL 7.3.1.11. CFG REG IA CTRL 7.3.1.12. CFG REG IA FN NUM 7.3.1.13. CFG REG IA WRDATA 7.3.1.14. CFG REG IA RDDATA 7.3.1.15. PRS CTRL 7.3.1.16. MSI PENDING CTRL 7.3.1.17. MSI PENDING 7.3.1.18. D-STATE STS 7.3.1.19. CFG RETRY CTRL
7.3.2. IP Debug Registers x
7.3.2.1. HIP Status 7.3.2.2. HIP BP CYCLES 7.3.2.3. HIA BP CYCLES 7.3.2.4. APP BP CYCLES 7.3.2.5. HIA RX BP CYCLES
7.3.3. IP Performance Monitor Registers x
7.3.3.1. PERFMON CTRL 7.3.3.2. TX MRD TLP 7.3.3.3. TX MWR TLP 7.3.3.4. TX MSG TLP 7.3.3.5. TX CFGWR TLP 7.3.3.6. TX CFGRD TLP 7.3.3.7. RX MRD TLP 7.3.3.8. RX MWR TLP 7.3.3.9. RX MSG TLP 7.3.3.10. RX CFGWR TLP 7.3.3.11. RX CFGRD TLP 7.3.3.12. TX MEM DATA 7.3.3.13. TX CPL DATA 7.3.3.14. RX MEM DATA 7.3.3.15. RX CPL DATA
A. Specifications x
A.1. P-Tile Specifications A.2. F-Tile Specifications A.3. R-Tile Specifications
A.1. P-Tile Specifications x
A.1.1. P-Tile Completion Buffer Size A.1.2. Power Management A.1.3. MSI and MSI-X
A.2. F-Tile Specifications x
A.2.1. F-Tile Completion Buffer Size A.2.2. Power Management
A.3. R-Tile Specifications x
A.3.1. R-Tile Completion Buffer Size A.3.2. Power Management A.3.3. MSI and MSI-X
B. Simulating the Design Example x
B.1. Testbench
B.1. Testbench x
B.1.1. Testbench Modules B.1.2. Test Driver Module B.1.3. PIO Design Example Testbench B.1.4. Root Port BFM
1. Introduction
2. Features
3. Getting Started with the AXI Streaming Intel® FPGA IP for PCI Express*
4. IP Architecture and Functional Description
5. AXI Streaming Intel® FPGA IP for PCI Express* Parameters
6. Interfaces and Signals
7. Register Descriptions
8. Document Revision History for the AXI Streaming Intel® FPGA IP for PCI Express* User Guide
A. Specifications
B. Simulating the Design Example

6.3.5.1.1. Application Logic Guidelines for the AXI Streaming TX Interface in HIP Native Mode (R-Tile)

The following guidelines must be considered by the Application logic:
  • Application logic must adhere to the requirements for the pX_app_ss_st_tx_ready and pX_app_ss_st_tx_valid signal behavior as outlined in the AXI4 Streaming Specifications.
  • Transmission of a TLP must be uninterrupted when the pX_app_ss_st_tx_ready is asserted, unless there is backpressure from the IP as indicated by the deassertion of pX_app_ss_st_tx_ready.
    Note: Failing to meet this guideline may cause the transmission of a TLP with an invalid LCRC.
  • For the 1x16 mode, the start of a command (header) can only happen in segment 0 (S0) or segment 2 (S2) (i.e. a given command cannot start on segment 1 (S1) or segment 3 (S3)).
  • For the 1x16 mode, the header for segment 2 is allowed depending on the utilization for segment 0 and segment 1. Refer to the table below for the allowed conditions. Note that the table does not include all the signals for the AXI-ST TX interface. It only shows the Header (H) and Data (D) combinations to highlight the valid cases where a command can be started on segment 2.
    Table 34.  TX AXI-ST HIP Native Mode Data Packing for x16 1024 Bits with 4 Segments
    S0 S1 S2 S3
    H, D - H, D -
    H, D D H, D D
    D - H, D D
    D D H, D -
  • For Configuration Mode 1 (2x8) and Configuration Mode 2 (4x4), the header for segment 1 is allowed depending on the utilization for segment 0. Refer to the table below for the allowed conditions. Note that the table does not include all the signals for the AXI-ST TX interface. It only shows the Header (H) and Data (D) combinations to highlight the valid cases where a TLP can be started on segment 1.
    Table 35.  TX AXI-ST HIP Native Mode Data Packing for x8
    S0 S1
    H, D H, D
    H, D D
    D H, D
  • For a single command spanning across multiple segments, the application logic needs to send the TLP in the order of the segment indices (segment S0 → S1 → S2 → S3 → S0).
  • If the length of the TLP being transmitted is greater than the segment size, the segment used to assert the pX_app_ss_st_tx_tuser_last_segment signal is dictated by the TLP length.
  • The app_ss_st_tx_tkeep signal must be used to qualify the byte-wise data on each segment to indicate if the content of the associated byte is valid. The invalid bytes are allowed only during the app_axi_st_tx_tlast cycle.
  • The maximum number of clock cycles allowed between the deassertion of pX_app_ss_st_tx_ready and pX_app_ss_st_tx_valid is 4 axi_st_clk cycles.

Example of the HIP Native mode packing scheme in Gen5x16 with a 1024-bit, 4-segment bus on the TX ASI-ST Interface:

1st Command with Data - Payload 16 Bytes

2nd Command with Data - Payload 32 Bytes

3rd Command with Data - Payload 64 Bytes

4th Command with Data - Payload 96 Bytes

5th Command with Data - Payload 128 Bytes

6th Command with Data - Payload 20 Bytes

Example of the HIP Native mode packing scheme in Gen5x8 with a 512-bit, 2-segment bus on the TX ASI-ST Interface:

1st Command with Data - Payload 16 Bytes

2nd Command with Data - Payload 32 Bytes

3rd Command with Data - Payload 96 Bytes

4th Command with Data - Payload 20 Bytes

AXI Streaming TX Interface ss_app_st_tx_tready Behavior in HIP Native Mode

The following timing diagram illustrates the behavior of ss_app_st_tx_tready, which is deasserted to pause the data transmission to the IP, and then reasserted. The application logic deasserts app_ss_st_tx_tvalid four clock cycles after ss_app_st_tx_tready is deasserted (from the point marked with the letter a to the point marked with the letter b). This is the maximum number of clock cycles allowed between the deassertion of ss_app_st_tx_tready and app_ss_st_tx_tvalid.

When the IP reasserts the ss_app_st_tx_tready signal (from the point marked with letter c to the point marked with letter d), the following two cases must be considered:
  • Case 1: If there is a TLP suspended due to the deassertion of ss_app_st_tx_tready, then the maximum number of clock cycles for app_ss_st_tx_tvalid to go high after the assertion of ss_app_st_tx_tready is one (as illustrated in the following figure).
  • Case 2: If there is no TLP suspended due to the deassertion of ss_app_st_tx_tready, then there is no requirement, and the application logic can reassert app_ss_st_tx_valid as soon as it has a TLP available to transmit. The application must not deassert app_ss_st_tx_valid during the packet transmission unless there is backpressure from the IP indicated by the deassertion of ss_app_st_tx_tready.
    Note: Failing to meet this guideline may cause the transmission of a TLP with an invalid LCRC.
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