6.1. Build Script
To build the PCIe-based example design, use the bin/dla_build_example_design.py script. You can use this script to create an example design with one or multiple Intel FPGA AI Suite IP instances.
The script generates a wrapper that wraps one or more IP instances along with adapters necessary to connect to the Terasic DE10-Agilex BSP or to the OPAE BSP ( Intel® Arria® 10).
When specifying an <architecture_file>, pay attention to the resource limitations on the FPGA, as well as the number of resources that the board support package (BSP) uses.
The dla_compiler tool includes a --fanalyze-area option to estimate the resources required for a single IP instance corresponding to an architecture file, as described in the Intel FPGA AI Suite Compiler Reference Manual.
Implementing two instances (as is the default for dla_build_example_design.py) requires twice the resources.
|Resources available on Intel® Arria® 10 1150 device||427200||2713||1518|
|Reasonable Target Utilization||80%||90%||90%|
|Resources needed for BSP||62000||330||0|
|Resources available for IP instances||280000||2115||1365|
The OPAE BSP used by the Intel PAC with Intel® Arria® 10 GC FPGA board is compatible only with bitstreams for accelerator function units (AFUs) compiled with Intel® Quartus® Prime Pro Edition Version 19.2. An AFU and its associated accelerator functions (AFs) are sometimes referred to as the green bitstream or green bits. For more details OPAE bitstream types, refer to Design Example Microarchitecture.
The DE10-Agilex design is only validated for use with Intel® Quartus® Prime Pro Edition Version 23.3. This Intel Agilex® 7 design does not use the Intel® Quartus® Prime partial reconfiguration feature, unlike the OPAE BSP. The Agilex device has significantly more resources and can support up to four IP instances.