Intel® FPGA AI Suite: PCIe-based Design Example User Guide

ID 768977
Date 12/01/2023
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Document Table of Contents
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2. About the PCIe* -based Design Example

The Intel FPGA AI Suite PCIe* -based design examples ( Intel® Arria® 10 and Intel Agilex® 7) demonstrate how the Intel® Distribution of OpenVINO™ toolkit and the Intel® FPGA AI Suite support the look-aside deep learning acceleration model.

The PCIe* -based design example ( Intel® Arria® 10) is implemented with the following components:

  • Intel® FPGA AI Suite IP
  • Intel Acceleration Stack for Intel® Xeon® CPU with FPGAs
  • Open Programmable Acceleration Engine (OPAE) components:
    • OPAE libraries
    • Intel FPGA Basic Building Blocks (BBB)
  • Intel® Distribution of OpenVINO™ toolkit
  • Intel Programmable Acceleration Card with Intel® Arria® 10 GX FPGA
  • Sample hardware and software systems that illustrate the use of these components

The PCIe-based design example ( Intel Agilex® 7) is implemented with the following components:

  • Intel® FPGA AI Suite IP
  • Intel® Distribution of OpenVINO™ toolkit
  • Terasic DE10-Agilex-B2E2 board
  • Sample hardware and software systems that illustrate the use of these components

This design example includes pre-built FPGA bitstreams that correspond to pre-optimized architecture files. However, the design example build scripts let you choose from a variety of architecture files and build (or rebuild) your own bitstreams, provided that you have a license permitting bitstream generation.

This design is provided with the Intel FPGA AI Suite as an example showing how to incorporate the IP into a design. This design is not intended for unaltered use in production scenarios. Any potential production application that uses portions of this example design must review them for both robustness and security.