Intel® FPGA AI Suite: PCIe-based Design Example User Guide

ID 768977
Date 4/05/2023

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5.7. Running the Ported OpenVINO™ Demonstration Applications

Some of the sample application demo from the OpenVINO™ toolkit for Linux Version 2021.4.2 have been ported to work with the Intel® FPGA AI Suite. These applications are built at the same time as the runtime when using the -build_demo flag to

The Intel® FPGA AI Suite runtime includes customized versions of the following demo applications for use with the Intel® FPGA AI Suite IP and plugins:

  • classification_sample_async
  • object_detection_demo_yolov3_async

Each demonstration application uses a different graph. The OpenVINO™ compiler falls back to CPU for unsupported sections of the graph. However, this is inefficient and can even cause available FPGA DDR memory to be exhausted if the graph execution switches between FPGA and CPU frequently enough and at memory-intensive portions of the graph.

You can use the following architecture description files located in the example_architectures/ directory of the Intel® FPGA AI Suite installation package to run the demos:
  • Intel® Arria® 10: A10_Generic.arch
  • Intel Agilex® 7: AGX7_Generic.arch

As specified in Programming the FPGA Device ( Intel Arria 10), you must program the FPGA device with the bitstream for the architecture being used. Each demonstration application includes a file specifying how to use it.

When the OpenVINO™ sample applications are modified to support the Intel® FPGA AI Suite, the Intel® FPGA AI Suite plugin used by OpenVINO™ needs to know how to find the .arch file describing the IP parameterization by using the following configuration key. The following C++ code is used in the demo for this purpose:

ie.SetConfig({ { DLIA_CONFIG_KEY(ARCH_PATH), FLAGS_arch_file } }, "FPGA");

The OpenVINO™ demonstration application hello_query_device does not work with the Intel® FPGA AI Suite due to low-level hardware identification assumptions.