Intel® FPGA AI Suite: PCIe-based Design Example User Guide

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ID 768977
Date 4/05/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA AI Suite PCIe-based Design Example User Guide 2. About the PCIe* -based Design Example 3. Getting Started with the Intel® FPGA AI Suite PCIe* -based Design Example 4. Building the Intel® FPGA AI Suite Runtime 5. Running the Design Example Demonstration Applications 6. Design Example Components 7. Design Example System Architecture for the Intel PAC with Intel® Arria® 10 GX FPGA A. Intel® FPGA AI Suite PCIe-based Design Example User Guide Archives B. Intel® FPGA AI Suite PCIe-based Design Example User Guide Document Revision History
4. Building the Intel® FPGA AI Suite Runtime x
4.1. CMake Targets 4.2. Build Options
5. Running the Design Example Demonstration Applications x
5.1. Exporting Trained Graphs from Source Frameworks 5.2. Compiling Exported Graphs Through the Intel FPGA AI Suite 5.3. Compiling the PCIe* -based Example Design 5.4. Programming the FPGA Device ( Intel® Arria® 10) 5.5. Programming the FPGA Device ( Intel Agilex® 7) 5.6. Performing Accelerated Inference with the dla_benchmark Application 5.7. Running the Ported OpenVINO™ Demonstration Applications
5.6. Performing Accelerated Inference with the dla_benchmark Application x
5.6.1. Inference on Image Classification Graphs 5.6.2. Inference on Object Detection Graphs 5.6.3. Additional dla_benchmark Options
5.6.2. Inference on Object Detection Graphs x
5.6.2.1. The mAP and COCO AP Metrics 5.6.2.2. Specifying Ground Truth 5.6.2.3. Example of Inference on Object Detection Graphs
5.7. Running the Ported OpenVINO™ Demonstration Applications x
5.7.1. Example Running the Object Detection Demonstration Application
6. Design Example Components x
6.1. Build Script 6.2. Example Architecture Bitstream Files 6.3. Software Components (Arria 10) 6.4. Software Interface to the BSP
6.1. Build Script x
6.1.1. Build Script Options 6.1.2. Script Flow
6.3. Software Components (Arria 10) x
6.3.1. OpenVINO™ FPGA Runtime Plugin 6.3.2. Intel FPGA AI Suite Runtime 6.3.3. OPAE Driver
7. Design Example System Architecture for the Intel PAC with Intel® Arria® 10 GX FPGA x
7.1. System Overview 7.2. Hardware
7.2. Hardware x
7.2.1. PLL Adjustment
1. Intel® FPGA AI Suite PCIe-based Design Example User Guide
2. About the PCIe* -based Design Example
3. Getting Started with the Intel® FPGA AI Suite PCIe* -based Design Example
4. Building the Intel® FPGA AI Suite Runtime
5. Running the Design Example Demonstration Applications
6. Design Example Components
7. Design Example System Architecture for the Intel PAC with Intel® Arria® 10 GX FPGA
A. Intel® FPGA AI Suite PCIe-based Design Example User Guide Archives
B. Intel® FPGA AI Suite PCIe-based Design Example User Guide Document Revision History

5.7. Running the Ported OpenVINO™ Demonstration Applications

Some of the sample application demo from the OpenVINO™ toolkit for Linux Version 2021.4.2 have been ported to work with the Intel® FPGA AI Suite. These applications are built at the same time as the runtime when using the -build_demo flag to build_runtime.sh.

The Intel® FPGA AI Suite runtime includes customized versions of the following demo applications for use with the Intel® FPGA AI Suite IP and plugins:

  • classification_sample_async
  • object_detection_demo_yolov3_async

Each demonstration application uses a different graph. The OpenVINO™ compiler falls back to CPU for unsupported sections of the graph. However, this is inefficient and can even cause available FPGA DDR memory to be exhausted if the graph execution switches between FPGA and CPU frequently enough and at memory-intensive portions of the graph.

You can use the following architecture description files located in the example_architectures/ directory of the Intel® FPGA AI Suite installation package to run the demos:
  • Intel® Arria® 10: A10_Generic.arch
  • Intel Agilex® 7: AGX7_Generic.arch

As specified in Programming the FPGA Device ( Intel Arria 10), you must program the FPGA device with the bitstream for the architecture being used. Each demonstration application includes a README.md file specifying how to use it.

When the OpenVINO™ sample applications are modified to support the Intel® FPGA AI Suite, the Intel® FPGA AI Suite plugin used by OpenVINO™ needs to know how to find the .arch file describing the IP parameterization by using the following configuration key. The following C++ code is used in the demo for this purpose: 

ie.SetConfig({ { DLIA_CONFIG_KEY(ARCH_PATH), FLAGS_arch_file } }, "FPGA");

The OpenVINO™ demonstration application hello_query_device does not work with the Intel® FPGA AI Suite due to low-level hardware identification assumptions.


Section Content
Example Running the Object Detection Demonstration Application

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