Intel® FPGA AI Suite: PCIe-based Design Example User Guide

ID 768977
Date 4/05/2023

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Document Table of Contents

6.1.1. Build Script Options

Table 5.  Build Script Options
Option Description
-a, --archs Path to Intel FPGA AI Suite IP Architecture Description File
-d, --archs-dir Path to directory that contains Architecture Description Files for you to interactively choose from (alternative to ‘-a’)
-ed, --example-design-id

To build for the Intel PAC with Intel® Arria® 10 GX FPGA board, specify 1.

To build for the Terasic DE10-Agilex board, specify 3.

(default: 1)

-n, --num-instances

Number of IP instances to build (default: 2).

For the Intel PAC with Intel® Arria® 10 GX FPGA board, this number must be either 1 or 2.

For the Terasic DE10-Agilex board, this number must be 1, 2, 3, or 4.

--build Option to perform compilation of the PCIe* design using Intel® Quartus® Prime after instantiation (default: False).

Path to hardware build directory where BSP infrastructure and generated RTL will be located.

(default: coredla/pcie_ed/platform/build_synth)

-s, --seed Seed to be used in compiling the design (default: 1).
--num-paths Number of top critical paths to report after compiling the design (default: 2000).
--qor-modules List of internal modules (instance names) from inside the IP to include in the QoR summary report.
-q, --quiet Run script quietly without printing the output of underlying scripts to the terminal.