Intel® FPGA AI Suite: PCIe-based Design Example User Guide

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ID 768977
Date 4/05/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA AI Suite PCIe-based Design Example User Guide 2. About the PCIe* -based Design Example 3. Getting Started with the Intel® FPGA AI Suite PCIe* -based Design Example 4. Building the Intel® FPGA AI Suite Runtime 5. Running the Design Example Demonstration Applications 6. Design Example Components 7. Design Example System Architecture for the Intel PAC with Intel® Arria® 10 GX FPGA A. Intel® FPGA AI Suite PCIe-based Design Example User Guide Archives B. Intel® FPGA AI Suite PCIe-based Design Example User Guide Document Revision History
4. Building the Intel® FPGA AI Suite Runtime x
4.1. CMake Targets 4.2. Build Options
5. Running the Design Example Demonstration Applications x
5.1. Exporting Trained Graphs from Source Frameworks 5.2. Compiling Exported Graphs Through the Intel FPGA AI Suite 5.3. Compiling the PCIe* -based Example Design 5.4. Programming the FPGA Device ( Intel® Arria® 10) 5.5. Programming the FPGA Device ( Intel Agilex® 7) 5.6. Performing Accelerated Inference with the dla_benchmark Application 5.7. Running the Ported OpenVINO™ Demonstration Applications
5.6. Performing Accelerated Inference with the dla_benchmark Application x
5.6.1. Inference on Image Classification Graphs 5.6.2. Inference on Object Detection Graphs 5.6.3. Additional dla_benchmark Options
5.6.2. Inference on Object Detection Graphs x
5.6.2.1. The mAP and COCO AP Metrics 5.6.2.2. Specifying Ground Truth 5.6.2.3. Example of Inference on Object Detection Graphs
5.7. Running the Ported OpenVINO™ Demonstration Applications x
5.7.1. Example Running the Object Detection Demonstration Application
6. Design Example Components x
6.1. Build Script 6.2. Example Architecture Bitstream Files 6.3. Software Components (Arria 10) 6.4. Software Interface to the BSP
6.1. Build Script x
6.1.1. Build Script Options 6.1.2. Script Flow
6.3. Software Components (Arria 10) x
6.3.1. OpenVINO™ FPGA Runtime Plugin 6.3.2. Intel FPGA AI Suite Runtime 6.3.3. OPAE Driver
7. Design Example System Architecture for the Intel PAC with Intel® Arria® 10 GX FPGA x
7.1. System Overview 7.2. Hardware
7.2. Hardware x
7.2.1. PLL Adjustment
1. Intel® FPGA AI Suite PCIe-based Design Example User Guide
2. About the PCIe* -based Design Example
3. Getting Started with the Intel® FPGA AI Suite PCIe* -based Design Example
4. Building the Intel® FPGA AI Suite Runtime
5. Running the Design Example Demonstration Applications
6. Design Example Components
7. Design Example System Architecture for the Intel PAC with Intel® Arria® 10 GX FPGA
A. Intel® FPGA AI Suite PCIe-based Design Example User Guide Archives
B. Intel® FPGA AI Suite PCIe-based Design Example User Guide Document Revision History

B. Intel® FPGA AI Suite PCIe-based Design Example User Guide Document Revision History

Document Version Intel® FPGA AI SuiteVersion Changes
2023.04.05 2023.1
  • Renamed thedlac command. The Intel® FPGA AI Suite compiler command is now dla_compiler.
  • Updated the Intel® Agilex™ product family name to "Intel Agilex® 7."
2022.12.23 2022.2
  • Removed the -f build script (dla_create_and_build_pcie_ed.py) option.
  • Renamed the benchmark_app to dla_benchmark.
  • Renamed dla_create_and_build_pcie_ed.py to dla_build_example_design.py
2022.05.26 2022.1.1
  • Updated description of how to run the OpenVINO demos.
2022.04.27 2022.1
  • Additional updates for Intel Agilex device support.
  • Updated the locations of graphs from the Getting Started tutorial.
2021.09.10 2021.2
  • Added updates for initial Intel Agilex device support.
2021.04.30 2021.1
  • Added additional demonstration programs.
  • Various corrections and updates.
2020.12.04 2020.2
  • Initial release.
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