AN 976: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Agilex® F-Tile Devices

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ID 763505
Date 1/10/2023
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Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Agilex™ F-tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Agilex™ F-tile Devices x
1.1. Hardware and Software Requirements 1.2. Hardware Setup 1.3. System Description 1.4. Interoperability Methodology 1.5. JESD204C Intel® FPGA IP and DAC Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. Summary 1.9. Document Revision History for AN 976: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Agilex™ F-Tile Devices
1.4. Interoperability Methodology x
1.4.1. Transmitter Data Link Layer 1.4.2. Transmitter Transport Layer (TL)
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Agilex™ F-tile Devices

1.4.2. Transmitter Transport Layer (TL)

To check the data integrity of the payload data stream through the transport layer, link layer and the PHY layer of the transmitter (TX) in JESD204C Intel® FPGA IP, the DAC is configured to PRBS23 test pattern. The DAC is also set to operate with the same configuration as set in the JESD204C Intel® FPGA IP. The PRBS generator in the JESD204C Intel® FPGA IP example design generates the PRBS23 pattern. The PRBS check in the DAC transport layer checks the PRBS23 data integrity.

The figure below shows the conceptual test setup for data integrity checking.

Figure 4. Data Integrity Check Using PRBS Checker
Table 2.  Transport Layer Test Cases
Test Case Objective Description Passing Criteria
TL.1 Checks the transport layer mapping of the data channel using the PRBS23 test pattern. The following signals in <ip_variant_name>_base.v is tapped:
  • j204c_tx_avst_ready
  • j204c_tx_avst_valid
  • j204c_tx_avst_data [(M*S*WIDTH_MULP*N)-1:0] 2 3 4 5

The txframe_clk is used as the sampling clock for the Signal Tap.

  • The j204c_tx_avst_valid and j204c_tx_avst_ready signals are asserted.
TL.2 Checks the data sample PRBS test using PRBS23 data. Generated PRBS23 patterns from FPGA or transmitter are checked using AD9081 API functions. The tests performs the following steps:
  • Checks for HMC7044 PLL lock.
  • Checks for AD9081 JRx link-up.
  • Calls sample PRBS test using API function.
  • Calls sample PRBS result using API function.
  • Checks for several channels passing. For example, if M = 8, then 2 virtual converters are mapped to each channel.

    M0M1 to channel 0, M1M2 to channel 1, etc.

The following registers in AD9081 are monitored for the PRBS23 test pattern:
  • JESD204C_RECEIVER_PRBS_LANE_UPDATE_ERROR_COUNT
  • JESD204C_RECEIVER_PRBS_LANE_ERROR_FLAG
  • JESD204C_RECEIVER_PRBS_LANE_INVALID_DATA_FLAG
Reading of datapath PRBS registers from 0x2063 to 0x2069 using the API functions as follows:
  • Error flag of I and Q channels should be '0'.
  • Invalid data flag of I and Q channels should be '0'.
  • Error counts of I and Q channels should be '0'.
Figure 5. PRBS Pattern Diagram
2 M is the number of converters.
3 S is the number of transmitter samples per converter per frame.
4 WIDTH_MULP is the data width multiplier between the application layer and transport layer.
5 N is the number of conversion bits per converter.
Level Two Title