AN 976: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Agilex® F-Tile Devices
1.6. Test Results
The following table contains the possible results and their definition.
| Result | Definition |
|---|---|
| PASS | The Device Under Test (DUT) was observed to exhibit conformant behavior. |
| PASS with comments | The DUT was observed to exhibit conformant behavior. However, an additional explanation of the situation is included (example: due to time limitations, only a portion of the testing was performed). |
| FAIL | The DUT was observed to exhibit non-conformant behavior. |
| Warning | The DUT was observed to exhibit behavior that is not recommended. |
| Refer to comments | From the observations, a valid pass or fail could not be determined. An additional explanation of the situation is included. |
The following table shows the results for test cases LL.1, LL.2, TL.1, and TL.2 with respective values of L, M, F, lane rate, sampling clock, link clock, and SYSREF frequencies.
| No. | L | M | F | DAC Sampling Clock (MHz) | FPGA Device Clock (MHz) | FPGA Frame Clock (MHz) | FPGA Link Clock (MHz) | Lane Rate (Gbps) | Link Layer Test (LL.1, LL.2) | Transport Layer Test (TL.1, TL.2) |
|---|---|---|---|---|---|---|---|---|---|---|
| 1 | 8 | 4 | 1 | 6000.00 | 375.00 | 375.00 | 375.00 | 24.75 | Pass | Pass |