F-Tile 25G Ethernet Intel® FPGA IP User Guide

ID 750198
Date 4/15/2024

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Document Table of Contents

4.1. Main Tab Options

Table 9.  Main Tab Parameter Settings
Parameter Range Default Setting Description
General Options
Ready Latency 0, 3 0

Selects the readyLatency value on the TX client interface. readyLatency is an Avalon® streaming interface property that defines the number of clock cycles of delay from when the IP core asserts the l1_tx_ready signal to the clock cycle in which the IP core can accept data on the TX client interface. Refer to the Avalon® Interface Specifications.

Selecting a latency of 3 eases timing closure at the expense of increased latency for the datapath.

If you set the readyLatency to 3 and turn on standard flow control, data might be delayed in the IP core while the IP core is backpressured.

Core Variant MAC+PCS+PMA, MAC+PCS+PMA Selects the primary blocks to include in the IP core variation.
  • MAC+PCS+PMA—The IP core generates with the capability of MAC, PCS, and PMA protocol layers.
PCS/PMA Options
Enable RS-FEC Enabled, Disabled Disabled When enabled, the IP core implements Reed-Solomon forward error correction (FEC).
Flow Control Options
Enable flow control Enabled, Disabled Disabled When enabled, the IP core implements flow control. When either link partner experiences congestion, the respective transmit control sends pause frames. Register settings in TX Flow Control Registers and RX Flow Control Registers control flow control behavior, including whether the IP core implements standard flow control or priority-based flow control.

If you turn on standard flow control and set the readyLatency to 3, data might be delayed in the IP core while the IP core is backpressured.

Number of queues 1-8 8 Specifies the number of queues used in managing flow control.
MAC Options
Enable link fault generation Enabled, Disabled Disabled When enabled, the IP core implements link fault signaling as defined in the IEEE 802.3-2012 IEEE Standard for Ethernet. The MAC includes a Reconciliation Sublayer (RS) to manage local and remote faults. When enabled, the local RS TX logic can transmit remote fault sequences in case of a local fault and can transmit IDLE control words in case of a remote fault.
Enable preamble passthrough Enabled, Disabled Disabled When enabled, the IP core is in RX and TX preamble pass-through mode. In RX preamble pass-through mode, the IP core passes the preamble and Start Frame Delimiter (SFD) to the client instead of stripping them out of the Ethernet packet. In TX preamble pass-through mode, the client specifies the preamble and provides the SFD to be sent in the Ethernet frame.
Enable TX CRC passthrough Enabled, Disabled Disabled When enabled, TX MAC does not insert the CRC-32 checksum in the out-going frame. In pass-through mode, the client must provide frames with at least 64 bytes, including the Frame Check Sequence (FCS). When disabled, the TX MAC computes and inserts a 32-bit FCS in the TX MAC frame.

This parameter is not available if you turn on Enable IEEE 1588.

Enable MAC statistic counters Enabled, Disabled Enabled When enabled, the IP core includes statistics counters that characterize TX and RX traffic.
10G/25G Rate Switching
Enable 10G/25G dynamic rate switching Enabled, Disabled Disabled If enabled, the IP core supports dynamic reconfiguration between the 10 Gbps and the 25 Gbps data rates.
Configuration, Debug and Extension Options
Reference clock frequency 156.25 156.25 Specifies the frequency of the transceiver CDR reference clock input in MHz.