Visible to Intel only — GUID: kcs1663133004693
Ixiasoft
Visible to Intel only — GUID: kcs1663133004693
Ixiasoft
8.5. Hard IP Registers
The Ethernet Reconfiguration interface (reconfig_eth) provides access to the Ethernet Hard IP Avalon® memory-mapped interface space. All addresses are byte-based addresses eventhough the register description specifies 32 bit boundary. Refer to the F-Tile Ethernet Hard IP Register Map to view the register map and register descriptions.
The Transceiver Reconfiguration interface provides access to the control and status registers of the Agilex™ 7 F-Tile transceiver. Refer to the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide for information about the transceiver register map and register descriptions.
The hard IP is configured in normal mode. The PPM of the refclk for the PMA should be the same value as the refclk for the SYS PLL. Therefore, the source for the two clocks should be the same.
Address | Name | Description | Access |
---|---|---|---|
0x0104 | qhip_scratch | Scratch register. 32 bits of scratch register space for testing. | RW |
0x0108 | eth_reset | IP soft reset register.
|
RW |
0x010C | eth_reset_status | IP reset status register. Not sticky bit, Includes the following fields:
|
RO |
0x0110 | phy_tx_pll_locked | TX PLL locked bit [7:0]. TX PLL used by the corresponding physical lane is locked. | RO |
0x0118 | pcs_status | PCS status. Includes the following field:
|
RO |
0x0128 | clk_tx_khz | i_clk_tx clock frequency in KHz. | RO |
0x012C | clk_rx_khz | i_clk_rx clock frequency in KHz. | RO |