F-Tile 25G Ethernet Intel® FPGA IP User Guide

ID 750198
Date 4/15/2024

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Document Table of Contents

2. About this IP

The F-Tile 25G Ethernet Intel FPGA IP implements the 25G & 50G Ethernet Specification, Draft 1.6 from the 25 Gigabit Ethernet Consortium and the IEEE 802.3by 25Gb Ethernet specification. The IP includes an option to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard. The MAC client side interface for the F-Tile 25G Ethernet Intel FPGA IP is a 64-bit Avalon® streaming interface. It maps to one 25.78125 Gbps transceiver. The IP optionally includes the IEEE 802.3-2018 Clause 108 Reed-Solomon forward error correction (RS-FEC) for support of IEEE802.3-2018 Clause 107 25GBASE-R PCS. IEEE 802.3 Clause 73 Auto-Negotiation and IEEE 802.3 Clause 74 CR/KR-FEC are not supported. Transceiver interface to 25GBASE-SR optical Physical Medium Dependent (PMD) transceiver is supported.

The F-Tile 25G Ethernet Intel FPGA IP provides standard media access control (MAC) and physical coding sublayer (PCS), Reed-Solomon Forward Error Correction (RS-FEC), and PMA functions shown in the following block diagrams. The PHY comprises the PCS, optional RS-FEC, and elective PMA.

Figure 1. F-Tile 25G Ethernet MAC, PCS, and PMA IP Block Diagram
Figure 2. F-Tile 10G/25G Ethernet MAC, PCS, and PMA IP Block Diagram

The following block diagram shows an example of a network application with F-Tile 25G Ethernet Intel FPGA IP MAC and PHY.

Figure 3. Example Network Application