F-Tile 25G Ethernet Intel® FPGA IP User Guide

ID 750198
Date 2/09/2023

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2.4. Performance and Resource Utilization

The following table shows the typical device resource utilization for selected configurations using the current version of the Intel® Quartus® Prime software. The timing margin for this IP core is a minimum of 15%.

Table 5.  IP Core FPGA Resource Utilization for F-tile 25G Ethernet Intel FPGA IP Core with MAC+PCS+PMA Core Variant for Intel® Agilex™ Devices
IP Core Settings


Dedicated Logic Registers

Block Memory Bits

RS-FEC disabled 9749 17937 177728
RS-FEC enabled 9846
Table 6.  IP Core Round Trip LatencyThe round trip latency values are based on the following definitions and assumptions:
  • Round trip latency is measured as the time taken for a packet to travel from TX Avalon® streaming interface to the RX Avalon® streaming interface with the IP core in serial loopback mode.
  • Latency values are obtained via simulation of the IP Core's example design generated using Intel® Quartus® Prime software v22.3. These values are expected to be different across different builds.
  • Synopsys's VCS simulator is used when measuring the following values. These values may differ across different simulators.

IP Core Settings

Latency (ns)

RS-FEC disabled 255
RS-FEC enabled 685