F-Tile 25G Ethernet Intel® FPGA IP User Guide

Download PDF
ID 750198
Date 2/09/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the F-Tile 25G Ethernet Intel FPGA IP User Guide 2. About this IP 3. Getting Started 4. F-tile 25G Ethernet Intel FPGA IP Parameters 5. Functional Description 6. Reset 7. Interfaces and Signal Descriptions 8. Control, Status, and Statistics Register Descriptions 9. Document Revision History for the F-tile 25G Ethernet Intel® FPGA IP User Guide
2. About this IP x
2.1. Release Information 2.2. Features 2.3. Device Family Support 2.4. Performance and Resource Utilization
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the IP Core Parameters and Options 3.3. Simulating the IP Core 3.4. Generated File Structure 3.5. Integrating Your IP Core in Your Design 3.6. Compiling the Full Design and Programming the FPGA
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.5. Integrating Your IP Core in Your Design x
3.5.1. Pin Assignments 3.5.2. Adding the F-tile Reference and System PLL Clocks Intel® FPGA IP 3.5.3. Placement Settings for the 25G Ethernet Intel FPGA IP Core
5. Functional Description x
5.1. F-tile 25G Ethernet Intel FPGA IP Core Functional Description 5.2. User Interface to Ethernet Transmission
5.1. F-tile 25G Ethernet Intel FPGA IP Core Functional Description x
5.1.1. F-tile 25G Ethernet Intel FPGA IP TX MAC Datapath 5.1.2. 25 GbE TX PCS 5.1.3. F-tile 25G Ethernet Intel FPGA IP Core RX MAC Datapath 5.1.4. Link Fault Signaling Interface 5.1.5. 25 GbE RX PCS 5.1.6. Flow Control
5.1.1. F-tile 25G Ethernet Intel FPGA IP TX MAC Datapath x
5.1.1.1. Frame Padding 5.1.1.2. Preamble Insertion 5.1.1.3. Inter-Packet Gap Generation and Insertion 5.1.1.4. Frame Check Sequence (CRC32) Insertion
5.1.3. F-tile 25G Ethernet Intel FPGA IP Core RX MAC Datapath x
5.1.3.1. IP Core Preamble Processing 5.1.3.2. IP Core Malformed Packet Handling 5.1.3.3. Length/Type Field Processing
5.1.3.3. Length/Type Field Processing x
5.1.3.3.1. Length Checking 5.1.3.3.2. RX CRC Checking and Dynamic Forwarding
5.1.6. Flow Control x
5.1.6.1. TX Pause/PFC Flow Control Frame Transmission Request 5.1.6.2. XON/XOFF Pause Frames
5.2. User Interface to Ethernet Transmission x
5.2.1. Order of Transmission 5.2.2. Bit Order For TX and RX Datapaths
7. Interfaces and Signal Descriptions x
7.1. TX MAC Interface to User Logic 7.2. RX MAC Interface to User Logic 7.3. Transceivers 7.4. Transceiver Reconfiguration Signals 7.5. Avalon® Memory-Mapped Management Interface 7.6. Miscellaneous Status and Debug Signals 7.7. Clock Signals 7.8. Reset Signals
8. Control, Status, and Statistics Register Descriptions x
8.1. TX MAC Registers 8.2. RX MAC Registers 8.3. Pause/PFC Flow Control Registers 8.4. Statistics Registers 8.5. Hard IP Registers
8.4. Statistics Registers x
8.4.1. TX Statistics Registers 8.4.2. RX Statistics Registers
1. About the F-Tile 25G Ethernet Intel FPGA IP User Guide
2. About this IP
3. Getting Started
4. F-tile 25G Ethernet Intel FPGA IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. Document Revision History for the F-tile 25G Ethernet Intel® FPGA IP User Guide

8.5. Hard IP Registers

The Ethernet Reconfiguration interface (reconfig_eth) provides access to the Ethernet Hard IP Avalon® memory-mapped interface space. All addresses are byte-based addresses eventhough the register description specifies 32 bit boundary. Refer to the F-tile Ethernet Hard IP Register Map to view the register map and register descriptions.

The Transceiver Reconfiguration interface provides access to the control and status registers of the Intel® Agilex™ F-tile transceiver. Refer to the F-tile Architecture and PMA and FEC Direct PHY IP User Guide for information about the transceiver register map and register descriptions.

Table 28.  Hard IP Registers
Address Name Description Access
0x0104 qhip_scratch Scratch register. 32 bits of scratch register space for testing. RW
0x0108 eth_reset IP soft reset register.
  • Bit[0]: eio_sys_rst
  • Bit[1]: soft_tx_rst
  • Bit[2]: soft_rx_rst
RW
0x010C eth_reset_status IP reset status register. Not sticky bit, Includes the following fields:
  • Bit[0]: rst_ack_n
  • Bit[1]: tx_rst_ack_n
  • Bit[2]: rx_rst_ack_n
RO
0x0110 phy_tx_pll_locked TX PLL locked bit [7:0]. TX PLL used by the corresponding physical lane is locked. RO
0x0118 pcs_status PCS status. Includes the following field:
  • Bit[2]: tx_lanes_stable
  • Bit[3]: rx_pcs_ready
RO
0x0128 clk_tx_khz i_clk_tx clock frequency in KHz. RO
0x012C clk_rx_khz i_clk_rx clock frequency in KHz. RO
Related Information
Level Two Title