AN 987: Static Update Partial Reconfiguration Tutorial: for Intel® Agilex™ F-Series FPGA Development Board
ID
749443
Date
10/24/2022
Public
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2.5.1. Step 1: Getting Started
2.5.2. Step 2: Create Design Partitions
2.5.3. Step 3: Allocate Placement and Routing Regions
2.5.4. Step 4: Define Personas
2.5.5. Step 5: Create Revisions
2.5.6. Step 6: Compile the Base Revision
2.5.7. Step 7: Set Up PR Implementation Revisions
2.5.8. Step 8: Change the SUPR Logic
2.5.9. Step 9: Program the Board
2.5.10. Modifying the SUPR Partition
2.1. Tutorial Requirements
This tutorial requires the following:
- Basic familiarity with the Intel® Quartus® Prime Pro Edition FPGA implementation flow and project files.
- Installation of Intel® Quartus® Prime Pro Edition version 22.3, with Intel® Agilex™ device support.
- For FPGA implementation, a JTAG connection with the Intel® Agilex™ F-Series FPGA development board on the bench.
- Download Reference Design Files.