AN 987: Static Update Partial Reconfiguration Tutorial: for Intel® Agilex™ F-Series FPGA Development Board

ID 749443
Date 10/24/2022

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2.2. Reference Design Overview

This reference design consists of one, 32-bit counter. At the board level, the design connects the clock to a 50MHz source, and then connects the output to four LEDs on the board. Selecting the output from the counter bits, in a specific sequence, causes the LEDs to blink at a specific frequency. The top_counter module is the SUPR region.
Figure 1. Flat Reference Design