Nios® V Processor Software Developer Handbook

ID 743810
Date 4/07/2025
Public
Document Table of Contents

9.2.1.2.3. Interrupt Dispatcher

The interrupt dispatcher checks the interrupt bits in mip register. If any interrupts are pending, it calls the appropriate ISR.
Interrupt prioritization is as follows:
  • All platform interrupts have higher priority than timer and software interrupts.
  • Among the 16 platform interrupts, platform interrupt 0 has the highest priority, and 15 the lowest.
  • This prioritization is inherent in the CLINT.

The interrupts dispatcher goes through the platform IRQs in mip register starting at platform IRQ0, and finds the first (highest priority) active platform IRQ. Then, the interrupts calls the corresponding registered ISR. After this ISR executes, the dispatcher begins scanning the platform IRQs again, starting at platform IRQ0. In this way, higher-priority interrupts are always processed before lower-priority interrupts. With all interrupts request fulfilled, the interrupt dispatcher returns to the trap handling code.

Figure 18. How Interrupt Dispatcher Handles Platform Interrupt

For more information about the Nios® V processor mip registers, refer to the Nios® V Processor Reference Manual.

For more information on registering an ISR, refer to the Interrupt Service Routines and Exception Handler chapter.