Nios® V Processor Software Developer Handbook

ID 743810
Date 4/07/2025
Public
Document Table of Contents

9.2.2.1. How the Hardware Works

The Nios® V processor can respond to traps including hardware interrupts, timer interrupt, software interrupts and software exceptions. When the Nios® V processor responds to a trap, it performs the following tasks:

  • Disables interrupts by clearing mstatus.mie and saves the previous value to mstatus.mpie.
  • Saves the next execution address in Machine Exception Program Counter (mepc).
  • Saves the cause of the trap in the Machine Cause register (mcause).
  • Switch to shadow register set through Shadow Register File Status register (msrfstatus) if enabled.
  • For exception – Transfers control to the exception dispatcher. The vector table base address (held in the mtvec register) contains the jump instruction to the exception dispatcher.
  • For interrupt – Transfer control to the interrupt ISR. Each interrupt vector contains the jump instruction to the individual ISRs. The processor calculates the interrupt vector, by adding vector table base address to four times the interrupt cause number.

Nios® V traps are vectored. It is implemented using a vector table, that holds jump instruction to the associated ISR. The interrupt cause code determines which jump instruction is executed.

All Nios® V processor trap types are precise. This means that after a trap is handled, the Nios® Vprocessor can re-execute the instruction that caused the trap.

For more information about Machine Trap Handling CSRs behaviour, refer to the Processor Reference Manual.