F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 4/07/2025
Public

Visible to Intel only — GUID: pio1661477700365

Ixiasoft

Document Table of Contents

6.3. Register Initialization

The F-Tile Triple-Speed Ethernet Intel® FPGA IP supports various types of interfaces commonly used by the following Ethernet solutions:
  • MII/GMII
  • 10-bit Interface
  • SGMII
  • 1000BASE-X
  • Management Data Input/Output (MDIO) for external PHY register configuration

When using the Triple-Speed Ethernet Intel® FPGA IP with an external interface, you must understand the requirements and initialize the registers.

Register initialization mainly performed in the following configurations:

  • External PHY Initialization using MDIO (Optional)
  • PCS Configuration Register Initialization
  • MAC Configuration Register Initialization