Visible to Intel only — GUID: opn1621239365408
Ixiasoft
Visible to Intel only — GUID: opn1621239365408
Ixiasoft
6.1.6. Deterministic Latency (Dword Offset 0xE1– 0xE3)
Dword Offset | Name | Bit | R/W | Description | HW Reset |
---|---|---|---|---|---|
0xE1 | dl_reset | [1] | RW | Deterministic latency (DL) soft reset.
Provides a soft reset to the deterministic latency block.
Note: This is not a self-clearing reset.
|
0x0 |
measure_valid | [0] | RO | Indicates whether the DL measurement values are valid.
|
0x0 | |
0xE2 | tx_delay | [20:0] | RO | TX datapath latency. Displays the TX datapath DL measurement values measured in the i_dl_sampling_clk cycles. measure_valid must be set prior taking the measurement. |
0x0 |
0xE3 | rx_delay | [20:0] | RO | RX datapath latency Displays the RX datapath DL measurement values measured in the i_dl_sampling_clk cycles. measure_valid must be set prior taking the measurement. |
0x0 |