Visible to Intel only — GUID: bhc1410932150399
Ixiasoft
Visible to Intel only — GUID: bhc1410932150399
Ixiasoft
8.3. Exposed Ports in the New User Interface
In MAC variation with internal FIFO buffers, the ready latency is two in both standalone and Platform Designer flow. The Platform Designer system inserts a timing adapter to change the ready latency to zero.
Port Name | I/O | Width | Recommended Termination Value |
---|---|---|---|
xon_gen | I | 1 | 1'b0 |
xoff_gen | I | 1 | 1'b0 |
magic_wakeup | O | 1 | Left open |
magic_sleep_n | I | 1 | 1'b1 |
ff_tx_crc_fwd | I | 1 | 1'b0 |
ff_tx_septy | O | 1 | Left open |
tx_ff_uflow | O | 1 | Left open |
ff_tx_a_full | O | 1 | Left open |
ff_tx_a_empty | O | 1 | Left open |
rx_err_stat | O | 18 | Left open |
rx_frm_type | O | 4 | Left open |
ff_rx_dsav | O | 1 | Left open |
ff_rx_a_full | O | 1 | Left open |
ff_rx_a_empty | O | 1 | Left open |
The following table lists the following ports that are exposed in the Platform Designer system for a design that has MAC variation without internal FIFO buffers.
Port Name | I/O | Width | Recommended Termination Value |
---|---|---|---|
xon_gen_<n> | I | 1 | 1'b0 |
xoff_gen_<n> | I | 1 | 1'b0 |
magic_wakeup_<n> | O | 1 | Left open |
magic_sleep_n_<n> | I | 1 | 1'b1 |
ff_tx_crc_fwd_<n> | I | 1 | 1'b0 |