2.1. Reconfiguration Sequence Flow
Figure 5. Multirate Reconfiguration Sequence FlowThe figure illustrates the multirate reconfiguration sequence flow of the controller when it receives input data stream and reference clock frequency, or when the transceiver is unlocked.
Figure 6. Reconfiguration Sequence FlowThe figure illustrates the Nios V software flow that involves the controls for I2C master and HDMI TX PHY.