2.3. Clocking Scheme
The HDMI PHY IP design example has the following clocking scheme:
- clk_fpga_b3_p is a 100 MHz fixed rate clock for running the Nios V processor and control functions. If the supplied frequency is correct, the user_led_g[1] toggles for every second.
- refclk_fmcb_p is a fixed rate reference clock for power-up calibration of the transceivers. It is 625 MHz by default but can be of any frequency.
- fmcb_gbtclk_m2c_p_0 is the TMDS clock for HDMI RX. This clock also drives the HDMI TX transceivers. If the supplied frequency is 148.5 MHz, the user_led_g[0] toggles for every second.