HDMI PHY IP Design Example User Guide

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ID 732781
Date 7/30/2025
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2.4. Hardware Setup

The HDMI PHY IP design example is HDMI 2.0b capable and performs a loop-through demonstration for a standard HDMI video stream.
Figure 7. Hardware Setup
To run the hardware test:
  1. Connect an HDMI-enabled device such as a graphics card with HDMI to the HDMI RX connector on the Bitec HDMI 2.0 daughter card, which routes the data to the transceiver RX block and HDMI RX.
  2. Connect a HDMI output device (e.g. monitor, pattern test checker) to the HDMI TX connector on the Bitec HDMI 2.0 daughter card, which routes the data from HDMI TX IP to transceiver TX block.

In the HDMI RX-TX Retransmit Design Example:

  1. , The design loops back RX data to TX.
  2. The HDMI sink decodes the port into a standard video stream and sends it to the clock recovery core.
  3. The HDMI RX decodes the video, auxiliary, and audio data to be looped back via AXI4-stream to the HDMI TX.
  4. The HDMI source port of the FMC daughter card transmits the image to a monitor.
  5. Press the cpu_resetn button once to perform system reset.
Note: If you want to use another Altera FPGA development board, you must change the device assignments and the pin assignments. The transceiver analog setting is tested for the Arria® 10 FPGA development kit and Bitec HDMI 2.0 daughter card. You may modify the settings for your own board.
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