Ashling* RiscFree* Integrated Development Environment (IDE) for Altera® FPGAs User Guide
ID
730783
Date
9/02/2025
Public
1. About this Document
2. Ashling RiscFree* IDE for Altera® FPGAs
3. Ashling Visual Studio Code Extension for Altera FPGAs
4. Ashling RiscFree* Integrated Development Environment (IDE) for Altera® FPGAs User Guide Archives
5. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Altera® FPGAs User Guide
A. Appendix
2.1. About the RiscFree* IDE for Altera® FPGAs IDE
2.2. Getting Started with the Ashling* RiscFree* IDE for Altera® FPGAs
2.3. Using Ashling* RiscFree* IDE for Altera® FPGAs with Nios® V Processor System
2.4. Using Ashling* RiscFree* IDE for Altera® FPGAs with Arm* Hard Processor System
2.5. Debugging Features with RiscFree* IDE for Altera® FPGAs
2.2.1. Installing RiscFree* IDE for Altera FPGAs
2.2.2. Getting Started with RiscFree* IDE for Altera® FPGAs
2.2.3. Creating the Project
2.2.4. Building the Application
2.2.5. Run and Debug Configurations in the RiscFree* IDE for Altera® FPGAs
2.2.6. Debug Information in the RiscFree* IDE for Altera® FPGAs
2.5.1. Debug Features in RiscFree* IDE
2.5.2. Processor System Debug
2.5.3. Heterogeneous Multicore Debug
2.5.4. Debugging µC/OS-II Application
2.5.5. Debugging FreeRTOS Application
2.5.6. Debugging Zephyr Application
2.5.7. Arm* HPS On-Chip Trace
2.5.8. Debugging the Arm* Linux Kernel
2.5.9. Debugging Target Software in an Intel® Simics Simulator Session
3.1. About the Ashling Visual Studio Code Extension
3.2. Getting Started with Ashling* Visual Studio Code Extension
3.3. Using Ashling* Visual Studio Code Extension with Nios® V Processor System
3.4. Using Ashling* Visual Studio Code Extension with Arm Hard Processor System
3.5. Debugging Features in Ashling* Visual Studio Code Extension
3.3.1. Creating Nios® V Processor BSP using Nios® V Processor BSP Generator
3.3.2. Creating Nios® V Processor Application Project using Nios® V App Generator
3.3.3. Importing Nios® V Processor Project
3.3.4. Building Nios® V Processor Project
3.3.5. Debugging a Nios® V Processor Project
3.3.6. Debugging Tools
A.2. Performing External Tools Configuration in Ashling* RiscFree* IDE for Altera® FPGAs
External tool configuration is a generic feature where you can configure the RiscFree* IDE to include tools based on your requirement.
To perform external tool configuration for juart terminal, follow these steps:
- Go to Run > External Tools > External Tools Configurations…. Double click Program to open a New_configuration window.
- Rename the configuration as Nios V JTAG UART Output.
- Browse and select the juart-terminal file in the following paths:
Operating System Path Windows* Quartus® Prime Software <Intel Quartus Prime installation directory>/quartus/bin64/juart-terminal.exe Quartus® Prime Programmer and Tools <Intel Quartus Prime installation directory>/qprogrammer/quartus/bin64/juart-terminal.exe Linux* Quartus® Prime Software <Intel Quartus Prime installation directory>/quartus/linux64/juart-terminal Quartus® Prime Programmer and Tools <Intel Quartus Prime installation directory>/qprogrammer/quartus/linux64/juart-terminal - Set the preferred arguments. In this example, set the arguments as follows:
- Connect to JTAG UART at cable 1: -c 1
- Connect to device 0: -d 1
- Connect to instance 0: -i 0
Note: JTAG device chain index varies according to your setup. Run jtagconfig --debug to obtain the latest device chain index numbering.Figure 170. External Tools ConfigurationNote: The steps are also applicable to other Nios® V tools (niosv-app and niosv-bsp) under <Intel Quartus Prime installation directory>/niosv/bin directory. These tools are not available for standalone RiscFree* IDE installation with the Quartus® Prime Programmer and Tools.