Ashling* RiscFree* Integrated Development Environment (IDE) for Altera® FPGAs User Guide

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ID 730783
Date 9/02/2025
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Document Table of Contents
Document Table of Contents x
1. About this Document 2. Ashling RiscFree* IDE for Altera® FPGAs 3. Ashling Visual Studio Code Extension for Altera FPGAs 4. Ashling RiscFree* Integrated Development Environment (IDE) for Altera® FPGAs User Guide Archives 5. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Altera® FPGAs User Guide A. Appendix
2. Ashling RiscFree* IDE for Altera® FPGAs x
2.1. About the RiscFree* IDE for Altera® FPGAs IDE 2.2. Getting Started with the Ashling* RiscFree* IDE for Altera® FPGAs 2.3. Using Ashling* RiscFree* IDE for Altera® FPGAs with Nios® V Processor System 2.4. Using Ashling* RiscFree* IDE for Altera® FPGAs with Arm* Hard Processor System 2.5. Debugging Features with RiscFree* IDE for Altera® FPGAs
2.1. About the RiscFree* IDE for Altera® FPGAs IDE x
2.1.1. Supported Devices 2.1.2. Quartus® Prime Software Support 2.1.3. Intel® Simics® Simulator for Intel® FPGAs Support
2.2. Getting Started with the Ashling* RiscFree* IDE for Altera® FPGAs x
2.2.1. Installing RiscFree* IDE for Altera FPGAs 2.2.2. Getting Started with RiscFree* IDE for Altera® FPGAs 2.2.3. Creating the Project 2.2.4. Building the Application 2.2.5. Run and Debug Configurations in the RiscFree* IDE for Altera® FPGAs 2.2.6. Debug Information in the RiscFree* IDE for Altera® FPGAs
2.2.1. Installing RiscFree* IDE for Altera FPGAs x
2.2.1.1. Bundled Installation with the Quartus® Prime Software 2.2.1.2. Standalone Installation
2.2.1.2. Standalone Installation x
2.2.1.2.1. Standalone Installation with Supported Quartus® Prime Software 2.2.1.2.2. Standalone Installation with the Quartus® Prime Programmer and Tools
2.2.2. Getting Started with RiscFree* IDE for Altera® FPGAs x
2.2.2.1. Ashling* RiscFree* IDE for Altera® FPGAs Workbench
2.2.2.1. Ashling* RiscFree* IDE for Altera® FPGAs Workbench x
2.2.2.1.1. Perspective, Editors, and Views 2.2.2.1.2. Starting a Project 2.2.2.1.3. Navigating the Project 2.2.2.1.4. Building the Project 2.2.2.1.5. Configuring the FPGA 2.2.2.1.6. Running the Project 2.2.2.1.7. Debugging the Project
2.2.3. Creating the Project x
2.2.3.1. Specifying the Project Location 2.2.3.2. Specifying the Project Name 2.2.3.3. Specifying the Project Type 2.2.3.4. Specifying the Configurations
2.2.5. Run and Debug Configurations in the RiscFree* IDE for Altera® FPGAs x
2.2.5.1. Opening the Run and Debug Configuration Dialog Boxes
2.2.6. Debug Information in the RiscFree* IDE for Altera® FPGAs x
2.2.6.1. Variables 2.2.6.2. Expressions 2.2.6.3. Registers 2.2.6.4. Memory 2.2.6.5. Disassembly
2.3. Using Ashling* RiscFree* IDE for Altera® FPGAs with Nios® V Processor System x
2.3.1. Importing Nios® V Processor Project 2.3.2. Building Nios® V Processor Project 2.3.3. Running a Nios® V Processor Project 2.3.4. Debugging a Nios® V Processor Project 2.3.5. Debugging Tools
2.3.4. Debugging a Nios® V Processor Project x
2.3.4.1. Download and Debug Nios® V Processor Application 2.3.4.2. Connect to a Running Nios® V Processor Application 2.3.4.3. Considerations when Debugging ROM-based Designs
2.3.4.3. Considerations when Debugging ROM-based Designs x
2.3.4.3.1. Unable to download (Load Image) 2.3.4.3.2. Unable to Set Software Breakpoint
2.3.5. Debugging Tools x
2.3.5.1. View Variables 2.3.5.2. Adding Expressions 2.3.5.3. View Memory 2.3.5.4. Disassembly View with Registers View/ Stepping into assembler functions 2.3.5.5. Hardware Breakpoint 2.3.5.6. Configuring Program Counter Manually
2.4. Using Ashling* RiscFree* IDE for Altera® FPGAs with Arm* Hard Processor System x
2.4.1. Pre-requisite for Debugging Arm* HPS Project 2.4.2. Importing Arm* HPS Project 2.4.3. Setting Debug Configurations and Downloading Arm* HPS Project Using RiscFree* IDE
2.5. Debugging Features with RiscFree* IDE for Altera® FPGAs x
2.5.1. Debug Features in RiscFree* IDE 2.5.2. Processor System Debug 2.5.3. Heterogeneous Multicore Debug 2.5.4. Debugging µC/OS-II Application 2.5.5. Debugging FreeRTOS Application 2.5.6. Debugging Zephyr Application 2.5.7. Arm* HPS On-Chip Trace 2.5.8. Debugging the Arm* Linux Kernel 2.5.9. Debugging Target Software in an Intel® Simics Simulator Session
2.5.1. Debug Features in RiscFree* IDE x
2.5.1.1. Viewing Global Variables 2.5.1.2. Launching Memory Browser 2.5.1.3. Debugger Console 2.5.1.4. Specifying the SVD File 2.5.1.5. Breakpoint Settings 2.5.1.6. JTAG UART Output Terminal
2.5.2. Processor System Debug x
2.5.2.1. GUI for Debugging
2.5.3. Heterogeneous Multicore Debug x
2.5.3.1. Importing Nios® V Processor and Arm* HPS Projects 2.5.3.2. Setting Core Configuration
2.5.7. Arm* HPS On-Chip Trace x
2.5.7.1. Trace Bar 2.5.7.2. Trace View
2.5.8. Debugging the Arm* Linux Kernel x
2.5.8.1. Preparing Linux for Kernel Debugging 2.5.8.2. Debugging the Arm* HPS Linux Kernel
3. Ashling Visual Studio Code Extension for Altera FPGAs x
3.1. About the Ashling Visual Studio Code Extension 3.2. Getting Started with Ashling* Visual Studio Code Extension 3.3. Using Ashling* Visual Studio Code Extension with Nios® V Processor System 3.4. Using Ashling* Visual Studio Code Extension with Arm Hard Processor System 3.5. Debugging Features in Ashling* Visual Studio Code Extension
3.1. About the Ashling Visual Studio Code Extension x
3.1.1. Supported Devices 3.1.2. Quartus® Prime Software Support
3.2. Getting Started with Ashling* Visual Studio Code Extension x
3.2.1. Installing Ashling* Visual Studio Code Extension 3.2.2. Getting Started with Ashling* Visual Studio Code Extension 3.2.3. Debug Configurations using Ashling* Visual Studio Code Extension for Altera FPGAS 3.2.4. Debug Information in the Ashling* Visual Studio Code Extension for Altera FPGAs
3.2.1. Installing Ashling* Visual Studio Code Extension x
3.2.1.1. Prerequisites 3.2.1.2. Installing Ashling* Visual Studio Code Extension for Altera FPGAs
3.2.2. Getting Started with Ashling* Visual Studio Code Extension x
3.2.2.1. Ashling* Visual Studio Code Extension Workbench
3.2.2.1. Ashling* Visual Studio Code Extension Workbench x
3.2.2.1.1. Perspective, Editors, and Views 3.2.2.1.2. Starting a Project 3.2.2.1.3. Navigating the Project 3.2.2.1.4. Building the Project 3.2.2.1.5. Configuring the FPGA 3.2.2.1.6. Debugging the Project
3.2.4. Debug Information in the Ashling* Visual Studio Code Extension for Altera FPGAs x
3.2.4.1. Variables 3.2.4.2. Expressions 3.2.4.3. Registers 3.2.4.4. Memory 3.2.4.5. Disassembly
3.3. Using Ashling* Visual Studio Code Extension with Nios® V Processor System x
3.3.1. Creating Nios® V Processor BSP using Nios® V Processor BSP Generator 3.3.2. Creating Nios® V Processor Application Project using Nios® V App Generator 3.3.3. Importing Nios® V Processor Project 3.3.4. Building Nios® V Processor Project 3.3.5. Debugging a Nios® V Processor Project 3.3.6. Debugging Tools
3.3.5. Debugging a Nios® V Processor Project x
3.3.5.1. Downloading and Debugging Nios® V Processor Application 3.3.5.2. Connecting to a Running Nios® V Processor Application 3.3.5.3. Considerations when Debugging ROM-based Designs
3.3.5.3. Considerations when Debugging ROM-based Designs x
3.3.5.3.1. Unable to download (Load Image) 3.3.5.3.2. Unable to Set Software Breakpoint
3.3.6. Debugging Tools x
3.3.6.1. View Variables 3.3.6.2. Adding Expressions 3.3.6.3. View Memory 3.3.6.4. Disassembly View with Registers View Stepping into Assembler Functions 3.3.6.5. Hardware Breakpoint 3.3.6.6. Configuring the Program Counter Manually
3.4. Using Ashling* Visual Studio Code Extension with Arm Hard Processor System x
3.4.1. Pre-requisite for Debugging Arm HPS Project 3.4.2. Importing Arm* HPS Project 3.4.3. Setting Debug Configurations and Downloading Arm HPS Project Using Visual Studio Code
3.5. Debugging Features in Ashling* Visual Studio Code Extension x
3.5.1. Debug Features in Ashling* Visual Studio Code Extension 3.5.2. Nios® V Processor System Debug 3.5.3. Heterogeneous Multicore Debug
3.5.1. Debug Features in Ashling* Visual Studio Code Extension x
3.5.1.1. Launching Memory Browser 3.5.1.2. Debugger Console 3.5.1.3. JTAG UART Output Terminal 3.5.1.4. Debugging RTOS
3.5.2. Nios® V Processor System Debug x
3.5.2.1. GUI for Debugging
3.5.3. Heterogeneous Multicore Debug x
3.5.3.1. Importing Projects 3.5.3.2. Debugging Multicore Projects (Multiple Nios® V Processor cores) 3.5.3.3. Debugging Multicore project ( Nios® V processor core and ARM HPS)
A. Appendix x
A.1. Optional Toolchain Configuration in Ashling* RiscFree* IDE for Altera® FPGAs A.2. Performing External Tools Configuration in Ashling* RiscFree* IDE for Altera® FPGAs A.3. Debugging with Command-Line Interface A.4. Help Content A.5. Open-Source Components in RiscFree* IDE
A.1. Optional Toolchain Configuration in Ashling* RiscFree* IDE for Altera® FPGAs x
A.1.1. Toolchain for Application and BSP A.1.2. Toolchain for Arm* Processor A.1.3. Modifying Toolchain Configuration
A.3. Debugging with Command-Line Interface x
A.3.1. Running Ashling* GBD Server A.3.2. Running GDB A.3.3. Nios® V Processor Example A.3.4. ARM HPS Core Example
1. About this Document
2. Ashling RiscFree* IDE for Altera® FPGAs
3. Ashling Visual Studio Code Extension for Altera FPGAs
4. Ashling RiscFree* Integrated Development Environment (IDE) for Altera® FPGAs User Guide Archives
5. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Altera® FPGAs User Guide
A. Appendix

2.5.6. Debugging Zephyr Application

When you debug the Nios® V processor application, you can view the Zephyr Mutex (Mutual Exclusion Object) List, Zephyr Semaphore List, and Zephyr Thread List.

To display details of Zephyr Mutex, Semaphore and Thread lists, enable the macros as below in the prj.conf file.

Table 10.  Zephyr Debug Configuration
Debug Information Macros Configuration Description
Enable Trace CONFIG_TRACING y
To enable all the tracing function.
Note: All tracing macros have dependency to CONFIG_TRACING.
Mutex List CONFIG_TRACING_OBJECT_TRACKING

y

 To enable object tracking for mutex.
Semaphore List To enable object tracking for semaphore.
Thread List CONFIG_DEBUG_THREAD_INFO y To display thread details.
The configuration is as shown below: 
CONFIG_TRACING=y
CONFIG_TRACING_OBJECT_TRACKING=y
CONFIG_DEBUG_THREAD_INFO=y

To debug Zephyr application, follow these steps:

Launch the Zephyr application debug.
  • To open the Zephyr Mutex List view, go to Window > Show View > Other > Zephyr Mutex List.
    Figure 63. Zephyr OS Mutex List View

    The Zephyr Mutex List tab shows details of all mutexes including handle, thread owner, lock count, priority, along with any wait threads related to each mutex.

  • To open the Zephyr Semaphore List view, go to Window > Show View > Other > Zephyr Sempahore List.
    Figure 64. Zephyr Sempahore List View

    The Zephyr Semaphore List tab shows details of all semaphores including handle, count, limit along with any wait threads related to each semaphore.

  • To open the Zephyr Thread List view, go to Window > Show View > Other > Zephyr Thread List.
    Figure 65. Zephyr OS Thread List View

    The Zephyr Thread List tab shows thread details including name, handle, priority, start of stack, stack size, and status details.

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