Ashling* RiscFree* Integrated Development Environment (IDE) for Altera® FPGAs User Guide
ID
730783
Date
9/02/2025
Public
1. About this Document
2. Ashling RiscFree* IDE for Altera® FPGAs
3. Ashling Visual Studio Code Extension for Altera FPGAs
4. Ashling RiscFree* Integrated Development Environment (IDE) for Altera® FPGAs User Guide Archives
5. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Altera® FPGAs User Guide
A. Appendix
2.1. About the RiscFree* IDE for Altera® FPGAs IDE
2.2. Getting Started with the Ashling* RiscFree* IDE for Altera® FPGAs
2.3. Using Ashling* RiscFree* IDE for Altera® FPGAs with Nios® V Processor System
2.4. Using Ashling* RiscFree* IDE for Altera® FPGAs with Arm* Hard Processor System
2.5. Debugging Features with RiscFree* IDE for Altera® FPGAs
2.2.1. Installing RiscFree* IDE for Altera FPGAs
2.2.2. Getting Started with RiscFree* IDE for Altera® FPGAs
2.2.3. Creating the Project
2.2.4. Building the Application
2.2.5. Run and Debug Configurations in the RiscFree* IDE for Altera® FPGAs
2.2.6. Debug Information in the RiscFree* IDE for Altera® FPGAs
2.5.1. Debug Features in RiscFree* IDE
2.5.2. Processor System Debug
2.5.3. Heterogeneous Multicore Debug
2.5.4. Debugging µC/OS-II Application
2.5.5. Debugging FreeRTOS Application
2.5.6. Debugging Zephyr Application
2.5.7. Arm* HPS On-Chip Trace
2.5.8. Debugging the Arm* Linux Kernel
2.5.9. Debugging Target Software in an Intel® Simics Simulator Session
3.1. About the Ashling Visual Studio Code Extension
3.2. Getting Started with Ashling* Visual Studio Code Extension
3.3. Using Ashling* Visual Studio Code Extension with Nios® V Processor System
3.4. Using Ashling* Visual Studio Code Extension with Arm Hard Processor System
3.5. Debugging Features in Ashling* Visual Studio Code Extension
3.3.1. Creating Nios® V Processor BSP using Nios® V Processor BSP Generator
3.3.2. Creating Nios® V Processor Application Project using Nios® V App Generator
3.3.3. Importing Nios® V Processor Project
3.3.4. Building Nios® V Processor Project
3.3.5. Debugging a Nios® V Processor Project
3.3.6. Debugging Tools
2.3.4.1. Download and Debug Nios® V Processor Application
You can download and debug the Nios® V processor software project on the targeted Intel FPGA using the RiscFree* IDE for Altera® FPGAs. To debug the project, follow these steps:
- Right-click the project folder (application or BSP) in the project explorer and select Debug As > Debug configurations.
- Select Ashling RISC-V Hardware Debugging > <Project Name>. Ensure the Project and C/C++ Application match your project name and project .elf file, respectively.
- Under the Main tab, for C/C++ Application, browse to select the application build .elf file. For example: hello.elf
Figure 14. Debug Configurations for Nios® V Processor—Main Tab.
- Under the Debugger tab, set these settings:
- Debug probe: Agilex SI/SoC Dev Kit (Name of the FPGA board/development kit)
- Transport type: JTAG
- JTAG frequency: 16 MHz
Figure 15. Debug Configurations for Nios® V Processor—Debugger Tab - Click Auto-detect Scan Chain to automatically detect JTAG scan chain information of the target device. Select the options from Device/Tap selection and Core selection.
- Leave all other settings as they are, including those in the Startup tab, as sensible defaults have been set.
Note: If you turn off Resume, you can debug from the processor initialization.Figure 16. Debug Configurations for Nios® V Processor — Turn off Resume
The example above shows that the program counter is at 0x3c0, which is displayed in the disassembly just after the reset vector. The processor jumps to 0x3c0, which is _start (the beginning of the Nios V processor initialization).
If you turn on Resume, you can debug from the user application.Figure 17. Debug Configurations for Nios® V Processor — Turn on ResumeThe example above shows that the program counter is at 0x37c, which is paused at the main function and is shown in the disassembly. The processor then jumps to 0x37c, which is paused at looper().
- Based on the OS you use, configure the OS Awareness settings as follows:
- Intel HAL: No OS Awareness configuration is required.
- Other OS: Under the OS Awareness tab, turn on Enable OS Aware Debugging, and select the OS version applicable to you as listed below:
- OS: μC/OS-II and Version: 2.93.0
- OS: FreeRTOS and Version: 10.5.0
- OS: Zephyr and Version: 3.2.0
Note: Nios® V processor does not support Linux OS.
Figure 18. Enabling OS Aware Debugging in RISC-V Hardware Debugging - Click Debug. RiscFree* IDE for Altera® FPGAs downloads the program to the target and you can find the console prints as shown in the following diagram.
Figure 19. Console Prints after Debug Connection is Successful
- Refer to the Debugging Features with RiscFree IDE section for further debugging.
Note: You can issue a debug reset using niosv-download -r command. This command only resets the Nios® V processor if the debug reset interface is connected to the Nios® V processor IP's reset input in your Platform Designer.Note: niosv-download (under <Intel Quartus Prime installation directory>/niosv/bin directory) is only available for the Quartus® Prime software. This tool is not available for standalone RiscFree* IDE for Altera® FPGAsRiscFree IDE installation with the Quartus® Prime Programmer and Tools