Ashling* RiscFree* Integrated Development Environment (IDE) for Altera® FPGAs User Guide
ID
730783
Date
9/02/2025
Public
1. About this Document
2. Ashling RiscFree* IDE for Altera® FPGAs
3. Ashling Visual Studio Code Extension for Altera FPGAs
4. Ashling RiscFree* Integrated Development Environment (IDE) for Altera® FPGAs User Guide Archives
5. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Altera® FPGAs User Guide
A. Appendix
2.1. About the RiscFree* IDE for Altera® FPGAs IDE
2.2. Getting Started with the Ashling* RiscFree* IDE for Altera® FPGAs
2.3. Using Ashling* RiscFree* IDE for Altera® FPGAs with Nios® V Processor System
2.4. Using Ashling* RiscFree* IDE for Altera® FPGAs with Arm* Hard Processor System
2.5. Debugging Features with RiscFree* IDE for Altera® FPGAs
2.2.1. Installing RiscFree* IDE for Altera FPGAs
2.2.2. Getting Started with RiscFree* IDE for Altera® FPGAs
2.2.3. Creating the Project
2.2.4. Building the Application
2.2.5. Run and Debug Configurations in the RiscFree* IDE for Altera® FPGAs
2.2.6. Debug Information in the RiscFree* IDE for Altera® FPGAs
2.5.1. Debug Features in RiscFree* IDE
2.5.2. Processor System Debug
2.5.3. Heterogeneous Multicore Debug
2.5.4. Debugging µC/OS-II Application
2.5.5. Debugging FreeRTOS Application
2.5.6. Debugging Zephyr Application
2.5.7. Arm* HPS On-Chip Trace
2.5.8. Debugging the Arm* Linux Kernel
2.5.9. Debugging Target Software in an Intel® Simics Simulator Session
3.1. About the Ashling Visual Studio Code Extension
3.2. Getting Started with Ashling* Visual Studio Code Extension
3.3. Using Ashling* Visual Studio Code Extension with Nios® V Processor System
3.4. Using Ashling* Visual Studio Code Extension with Arm Hard Processor System
3.5. Debugging Features in Ashling* Visual Studio Code Extension
3.3.1. Creating Nios® V Processor BSP using Nios® V Processor BSP Generator
3.3.2. Creating Nios® V Processor Application Project using Nios® V App Generator
3.3.3. Importing Nios® V Processor Project
3.3.4. Building Nios® V Processor Project
3.3.5. Debugging a Nios® V Processor Project
3.3.6. Debugging Tools
3.2.1.2. Installing Ashling* Visual Studio Code Extension for Altera FPGAs
Note: To select a specific Quartus® Prime version, you can either modify the default Quartus® Prime environment variables or open Ashling* Visual Studio Code Extension through the Nios® V Command Shell. Launching Ashling* Visual Studio Code Extension via the Nios® V Command Shell ensures that the Ashling: InstallationPath is automatically configured to the desired Quartus® Prime version based on the environment settings defined in the Nios® V Command Shell.
- Open the Start Menu and search for Nios® V Command Shell. Then, launch it.
- Type the following code to launch Ashling* Visual Studio Code Extension.
$ code.
- Click Extensions icon in the Activity bar.
Figure 90. Extensions Icon in Activity Bar
- Navigate to Views and More Actions > Primary Side Bar > Install from VSIX….
Figure 91. Views and More Actions in Primary Side BarFigure 92. Install from VSIX
- Browse to <Quartus Prime Installation directory>/riscfree/vscode/<Ashling VSCode For Altera FPGA.vsix extension and click Install.
- Once the extension is installed, the Ashling icon appears in the Activity bar.
Note: After the installation process, ensure that the C/C++, CMake, CMake Tools, debug-tracker-vscode, Embedded Tools, Peripheral Viewer, and Memory View extensions are also installed.Figure 93. Installed Ashling* Visual Studio Code Extension for Altera FPGAs
- Click the Ashling icon under QUICK SETTINGS and click Verify and Configure Dependencies to set the debug environment. Ashling* Visual Studio Code Extension verifies the presence of Quartus® Prime and Ashling* RiscFree* IDE for Altera® FPGAs in the machine and configures the path for build tools (Make, CMake, etc.), compiler (Nios V GNU GCC toolchain), and debugger (GDB, Ashling GDB Server, Intel JTAG Server, etc.).
Figure 94. Verify and Configure Dependencies
If the extension found the Quartus® Prime and Ashling* RiscFree* IDE for Altera® FPGAs path successfully, the Ashling* Visual Studio Code Extension reports successful verification in the OUTPUT view.
Note: Ensure that all dependencies have passed the verification process. If any dependency fails, please consult with support.
Figure 95. Output of Verify and Configure Dependencies
[3:57:46 PM] Starting Quartus installation search... [3:57:48 PM] Checking environment variables: [3:57:48 PM] QUARTUS_ROOTDIR: C:\altera_pro\25.1\quartus [3:57:48 PM] QUARTUS_ROOT: not set [3:57:48 PM] ALTERA_ROOT: not set [3:57:48 PM] ✅ Found Quartus installation(s) at: C:\altera_pro\25.1\quartus [3:57:48 PM] Searching for RiscFree installation... [3:57:50 PM] Checking for RiscFree at: C:\altera_pro\25.1\riscfree [3:57:50 PM] ✅ Valid RiscFree installation found at: C:\altera_pro\25.1\riscfree [3:57:50 PM] Verifying RiscFree toolchain... [3:57:52 PM] Setting up VS Code configuration... [3:57:53 PM] ✅ Setup completed successfully! [3:57:53 PM] Checking toolchain components... [3:57:53 PM] Checking Ashling SDK Installation ================================ [3:57:53 PM] Verifying Build Tools ------------------------------- Checking CMake........ ✅ Location: C:\altera_pro\25.1\riscfree\build_tools\cmake\bin\cmake.exe Getting version........ 3.30.2 Checking Make........ ✅ Location: C:\altera_pro\25.1\riscfree\build_tools\bin\make.exe Checking Ashling CLI........ ✅ Location: C:\altera_pro\25.1\riscfree\cli\ashling-cli.exe [3:57:55 PM] Verifying Debug Tools ------------------------------- Checking ARM GDB Server........ ✅ Location: C:\altera_pro\25.1\riscfree\debugger\gdbserver-arm\ash-arm-gdb-server.exe Checking RISC-V GDB Server........ ✅ Location: C:\altera_pro\25.1\riscfree\debugger\gdbserver-riscv\ash-riscv-gdb-server.exe Checking QEMU RISC-V........ ✅ Location: C:\altera_pro\25.1\riscfree\qemu\qemu-system-riscv32.exe Getting version........ 9.0.2 [3:57:56 PM] Verifying RISC-V Toolchain ------------------------------------ Checking RISC-V GCC (32-bit)........ ✅ Location: C:\altera_pro\25.1\riscfree\toolchain\riscv32-unknown-elf\bin\riscv32-unknown-elf-gcc.exe Getting version........ 13.2.0 Checking RISC-V G++ (32-bit)........ ✅ Location: C:\altera_pro\25.1\riscfree\toolchain\riscv32-unknown-elf\bin\riscv32-unknown-elf-g++.exe Checking RISC-V GDB (32-bit)........ ✅ Location: C:\altera_pro\25.1\riscfree\toolchain\riscv32-unknown-elf\bin\riscv32-unknown-elf-gdb.exe Getting version........ Version unknown [3:57:58 PM] Verifying ARM Toolchain --------------------------------- Checking ARM GDB (AArch64 ELF)........ ✅ Location: C:\altera_pro\25.1\riscfree\toolchain\Arm\aarch64-none-elf\bin\aarch64-none-elf-gdb.exe Getting version........ Version unknown [3:57:58 PM] Summary ======= Components Found: 10/10 ✅ All components verified successfully
If the extension couldn’t locate the Quartus® Prime and Ashling* RiscFree* IDE for Altera® FPGAs path automatically, the Ashling* Visual Studio Code Extension extension prompts the Browse Now dialogue box. You are required to browse and select the location of the missing component(s).
For example, the Ashling* RiscFree* IDE for Altera® FPGAs folder can be found within the Quartus® Prime installation folder. (<Quartus Installation Directory>\altera_pro\XX.Y\riscfree).
Figure 96. RiscFree Setup
The following messages appear when the missing component is found and configured successful by the extension.
Figure 97. Verify and Configure Dependencies Successful