1. About the RiscFree* IDE 2. Installation and Setup 3. Getting Started with RiscFree* IDE 4. Debug Setup for Nios® V Processor System 5. Debug Setup for Arm* Hard Processor System 6. Debugging with RiscFree* IDE 7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives 8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide A. Appendix
8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide
1. About the RiscFree* IDE
|Intel® Quartus® Prime Design Suite 22.3|
RiscFree* is Ashling’s Eclipse* C/C++ Development Toolkit (CDT) based integrated development environment (IDE) for Intel® FPGAs Arm* -based HPS and RISC-V based Nios® V processors.
The RiscFree* IDE provides a complete, seamless environment for C and C++ software development and has the following features:
- Eclipse* CDT based IDE with full source and project creation, editing, build, and debug support using the RISC-V GNU compiler collection (GCC) toolchain.
- Project Manager and Build Manager including Make and CMake support with rapid import, build, and debug of application frameworks created using the Intel® Quartus® Prime software.
- RISC-V GNU GCC toolchain with support for newlib or picolibc run-time libraries using the Nios® V Hardware Abstraction Layer (HAL) API for hardware access.
- Integrated support for Intel® FPGA Download Cable II JTAG debug probe.
- ROM or RAM based debugging support, for example, hardware breakpoints for flash-based support.
- High-level Register Viewer based on industry standard System View Description (SVD) files.
- Integrated serial terminal.